Bit-level systolic implementation of discrete orthogonal transforms

Nayak, S. S.; Murty, M. N.; Panda, H.

doi:10.1016/s0165-1684(01)00021-4

Cited by 3 publications

(2 citation statements)

References 15 publications

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“…The first transform component y 0 is available after (N+2n-2) clock cycles. Structure of [7] Structure of [8] Computation time The set up time to load the input words in the parallel -serial shift registers is ignored in the estimation of computation time.…”

Section: Proposed Systolic Architecturementioning

confidence: 99%

4-Bit Serial-Parallel Multiplier and Bit-Level Systolic Architecture for Implementation of Discrete Orthogonal Transforms

Murty

Nayak

Padhy

et al. 2012

Communications in Computer and Information Science

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Highly efficient arithmetic operations are necessary to achieve the desired performance in many real-time systems and digital image processing applications. In all these applications, one of the important arithmetic operations frequently performed is to multiply and accumulate with small computational time. In this paper, a serial -parallel multiplier, which can be used to perform either signed or unsigned multiplications, is presented. In this multiplier one factor B(n) is fed serially with word length n=4 while the other A(m) is stored in parallel with number of bits m=4. Baugh-Wooley algorithm necessitates complementation of last bit of each partial product except the last partial product in which all but the last bit are complemented. In the proposed algorithm all bits of the last partial product are complemented. This modification results in considerable reduction in hardware compared to Baugh-Wooley multiplier. This multiplier can be used for implementation of discrete orthogonal transforms, which are used in many applications, including image and signal processing. Also a fully pipelined 2-D bit-level systolic architecture is presented for efficient implementation of discrete orthogonal transforms using a serial-parallel matrix-vector multiplication scheme. A comparison with similar structures has shown that the proposed structure requires less computation time.

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Section: Proposed Systolic Architecturementioning

confidence: 99%

4-Bit Serial-Parallel Multiplier and Bit-Level Systolic Architecture for Implementation of Discrete Orthogonal Transforms

Murty

Nayak

Padhy

et al. 2012

Communications in Computer and Information Science

View full text Add to dashboard Cite

show abstract

“…These convolution-based architectures can be categorized as singleor multistage pipeline architectures. The architectures proposed in [12]- [16] are single-stage architectures in which the DCT computation is performed using a recursive pyramid algorithm (RPA) [20] that results in a reduced memory space requirement for the architectures.…”

Section: Introductionmentioning

confidence: 99%

An Area efficient and more accurate DA-based DCT with more compression rate

Gulla¹,

Rajasekhar²

2012

IOSRJVSP

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Bit-Level Systolic Architecture for a Matrix-Matrix Multiplier

Murty

Nayak

Padhy

et al. 2012

IJEEE

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View full text Add to dashboard Cite

Highly efficient arithmetic operations are necessary to achieve the desired performance in many real-time systems and digital image processing applications. In all these applications, one of the important arithmetic operations frequently performed is to multiply and accumulate with small computational time. In this paper, a 4-bit serial - parallel multiplier, which can perform both positive and negative multiplications, is presented. Baugh-Wooley algorithm necessitates complementation of last bit of each partial product except the last partial product in which all but the last bit are complemented. In the proposed algorithm all bits of the last partial product are complemented. This modification results in considerable reduction in hardware compared to Baugh-Wooley multiplier. This multiplier can be used for implementation of discrete orthogonal transforms, which are used in many applications, including image and signal processing. This paper presents a 2D bit-level systolic architecture for a matrixmatrix multiplier. A comparison with similar structures has shown that the proposed structure performs better.

show abstract

Bit-level systolic implementation of discrete orthogonal transforms

Cited by 3 publications

References 15 publications

4-Bit Serial-Parallel Multiplier and Bit-Level Systolic Architecture for Implementation of Discrete Orthogonal Transforms

4-Bit Serial-Parallel Multiplier and Bit-Level Systolic Architecture for Implementation of Discrete Orthogonal Transforms

An Area efficient and more accurate DA-based DCT with more compression rate

Bit-Level Systolic Architecture for a Matrix-Matrix Multiplier

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