Continuous efforts to shrink the physical size of transistors enable the integration of a larger number of transistors on a single chip. Today, it is feasible to fabricate a single SRAM cell in a 0.04999-µm 2 area [1]. However, as the transistors are aggressively scaled down, the impacts of the process-induced random variations on the device performance are dramatically increased [2]. The term "process-induced random variations" indicates that the process/fabrication steps such as doping, lithography, etching, chemical mechanical polishing (CMP), and so on, induce these random variations [3]. The well-known random variation sources caused by the aforementioned process steps are random dopant fluctuations (RDF) [4] [also known as random dopant distributions (RDD)] [5], line edge roughness (LER) [6], work function variations (WFV) [7] (also known as metal grain granularity (MGG) [8]), and oxide thickness variations [9]. Aforementioned random variations cause variations in parameters such as effective channel length and threshold voltage of each transistor. Then, the mismatches in the effective channel lengths and threshold voltages between two neighboring transistors cause degradations in the stability of the SRAM cells, which consist of a few transistors (e.g., 6 transistors for 6T SRAM cell) [10]. This is because each transistor of a single SRAM cell should be balanced in order to make it stable for the read/write/retention operations [11]. Further detailed information about how to balance the different transistors of a single SRAM cell, and how badly the stabilities of the SRAM cells are degraded by process-induced variations, will be provided later.Since random variations significantly affect the performance of SRAM cells, it is irrefutable that random variations are one of the key factors in the SRAM cell design. Furthermore, it is important to look for "random variation"-tolerant SRAM designs because random variations cannot be controlled, as systematic variations are controlled [12]. In order to find the random-variation-tolerant SRAM cell designs, understanding how the SRAM cell operates and how the process-induced