Bit-Sliding: A Generic Technique for Bit-Serial Implementations of SPN-based Primitives

Jean, Jérémy; Moradi, Amir; Peyrin, Thomas; Sasdrich, Pascal

doi:10.1007/978-3-319-66787-4_33

Cited by 43 publications

(80 citation statements)

References 25 publications

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“…To support both encryption and decryption operations, the unified architecture sharing common datapath for both encryption and decryption operations was proposed in [5]. However, the implementations may not be suitable for low-end devices, such as passive RFID tags, where the area and power consumption are limited [6,7]. In order to dramatically reduce the area and power consumption of the circuit, serial implementation is considered.…”

Section: Previous Work On Asicmentioning

confidence: 99%

“…e serial hardware operates in units of one bit or a few bits. is compact hardware is suitable for resource-constrained devices such as passive RFID tags with limited chip area and peak power consumption [7,15,17].…”

Section: Hardware Implementationmentioning

confidence: 99%

“…Since this type of shift register does not have MUX for input selection of ip-op, the area of the ip-op is reduced to approximately 60-70% of the conventional ip-op [7]. is scheme is e ective for overall area reduction because registers occupy a large portion of HIGHT hardware.…”

Section: Bit-serial Implementationmentioning

confidence: 99%

“…e 64-bit text is divided into eight 1-byte words as shown in Figure 1. e even words (X [0], X [2], X [4], and X [6]) are processed in even steps and the odd words (X [1], X [3], X [5], and X [7]) are processed in odd steps. To perform the round function of bit-serial encryption, one of the eight indices in the text register is selected for each round.…”

Section: Bit-serial Implementationmentioning

confidence: 99%

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Compact Implementations of HIGHT Block Cipher on IoT Platforms

Kim

Cho

Choi

et al. 2019

Security and Communication Networks

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Recent lightweight block cipher competition (FELICS Triathlon) evaluates efficient implementations of block ciphers for Internet of things (IoT) environment. In the competition, the implementation of HIGHT block cipher achieved the most efficient lightweight block cipher, in terms of code size (ROM), memory (RAM), and execution time. In this paper, we further investigate lightweight features of HIGHT block cipher and present the optimized implementations of both software and hardware for low-end IoT platforms, including resource-constrained devices (8-bit AVR and 32-bit ARM Cortex-M3) and application-specific integrated circuit (ASIC). By using proposed optimization methods, the implemented HIGHT block cipher shows better performance compared to previous state-of-the-art implementations.

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Section: Previous Work On Asicmentioning

confidence: 99%

Section: Hardware Implementationmentioning

confidence: 99%

Section: Bit-serial Implementationmentioning

confidence: 99%

Section: Bit-serial Implementationmentioning

confidence: 99%

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Compact Implementations of HIGHT Block Cipher on IoT Platforms

Kim

Cho

Choi

et al. 2019

Security and Communication Networks

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“…The clock consumption is considered one of the problems that face the information security experts. The more time the encryption system takes to encrypt the data, the more chances increase for the hackers to break into the system [17,18]. This paper discusses the design, analysis and implementation of pipelined method to reduce the consumed numbers of clocks and speed up the processes [19].…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of Pipelined AES Encryption System using FPGA

Nabil¹,

Khalaf²,

Hassan³

2020

IJRTE

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Nowadays, the data encryption became very important because of the usage of the data transmission in all the filed. The Advanced Encryption Standard (AES) that known as Rijndael algorithm is one of the most common encryption algorithms. The AES consists of 9 rounds in addition to the initial and final rounds that makes the AES consumes much time for encrypting the data. Of course the time consumption is considered one of the problems that face the information security. The more time the encryption system consumes to encrypt the data, the more chances increase for the hackers to break into the system. In this work, we find a new technique that can be used to increase the performance speed of the advanced encryption standard. The proposed algorithm methodology depends on the pipelined processing method for the processing time reduction. The paper includes a discussion of the design, the analysis and the implementation using Field Programmable Gate Array (FPGA) of the pipelined method to reduce the consumed numbers of clocks and speed up the processes. The AES is used to protect information and encrypt sensitive data and used in satellites, missiles, military application and other critical application. The paper describes the AES encryption system algorithm and the implementation of both the normal processing and the pipelined processing, and finally a comparison between the two algorithms.

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