Bit-swapping LFSR for low-power BIST

Abu-Issa, Abdallatif; Quigley, Steven F.

doi:10.1049/el:20083481

Cited by 33 publications

(10 citation statements)

References 2 publications

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“…The BIST block consists of a modified DS LFSR design (designed using a Bit-Swapping LFSR [13] and Dual Speed LFSR [1] blocks), Memory under test, Reference memory (ROM) and a comparator. The modified DS-LFSR generates test patterns with reduced switching activity consisting of single bit change vectors and the frequency of transitions among consecutive test patterns is also reduced.…”

Section: Proposed Infrastructurementioning

confidence: 99%

“…The BS LFSR [13] is a kind of LFSR which can reduce switching activity between consecutive test patterns during test application by swapping two neighboring bits using a multiplexer. Based on select line value of the multiplexer, this swapping process is done [3].…”

Section: A Modified Dual Speed Lfsrmentioning

confidence: 99%

“…Fig.3 shows the modified DS-LFSR design. The use of BS-LFSR lowers the transition density at the circuit input driven by slow BS LFSR [13] leading to a reduction in heat dissipation during test application with slight area over head. Dual Strategy is employed to reduce both Average and Peak power [7].…”

Section: A Modified Dual Speed Lfsrmentioning

confidence: 99%

See 2 more Smart Citations

A low power built in repair analyzer for word oriented memories with optimal repair rate

Banupriya¹,

Chandrakala²

2014

2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE)

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High density memories are more prone to faults caused due to process variations or manufacturing defects. Such faults reduce yield as well as reliability. The failures in such memories are expensive due to wastage of large die area. These faults can be repaired by redundant memory locations. This paper presents a Built In Repair Analyzer for memory arrays using redundancy. A Built In Self Test block detects faults occurred, the Syndrome Storing Detector block distinguishes temporary and permanent faults. The permanent faults are alone repaired thus utilizing spare resources efficiently. The Must- Repair-Analysis (MRA) technique is done on fly during test, it stores faulty addresses and final analysis is done to find a solution to eliminate the analyzed faults. The BIRA module executes an efficient Redundancy Analysis algorithm to generate possible repair solutions. Further, power consumption is reduced using a novel low power Linear Feedback Shift Register (LFSR) which is a combination of Bit Swapping LFSR (BS-LFSR) and Dual Speed LFSR (DS-LFSR). The modified Dual Speed LFSR (MDS-LFSR) consists of two BS-LFSR's, one is the slow speed BS-LFSR andanother is the normal speed BS-LFSR each has independent clock rates. The modified DS LFSR lowers the transition density at the input side. Thus it reduces overall switching activity in Memory Under Test as well as reduces frequency of transitions of input patterns finally reducing the overall test power.

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Section: Proposed Infrastructurementioning

confidence: 99%

Section: A Modified Dual Speed Lfsrmentioning

confidence: 99%

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A low power built in repair analyzer for word oriented memories with optimal repair rate

Banupriya¹,

Chandrakala²

2014

2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE)

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“…2). In this arrangement, the output of the two cells will have its transition count reduced by T saved = 2 (n-2) transitions [23]. Since the two cells originally produce 2 × 2 n-1 , then the resulting percentage saving is T saved% = 25%.…”

Section: Lemmamentioning

confidence: 99%

LT-PRPG: Power minimization technique for test-per-scan BIST

Abu-Issa

Quigley

2008

2008 3rd International Conference on Design and Technology of Integrated Systems in Nanoscale Era

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This paper presents a new Low Transition PseudoRandom Pattern Generator (LT-PRPG) for test-per-scan Built-In Self-Test (BIST) applications. The proposed LT-PRPG is composed of a LFSR and a 2x1 multiplexer. When used to generate test patterns for test-per-scan BIST, it reduces the number of transitions that occur at scan inputs during scan shift operations and hence reduces switching activity in the CircuitUnder-Test (CUT) during the test application. Various properties of the proposed LT-PRPG and the methodology of the design are presented in this paper. Experimental results for the ISCAS'89 benchmark circuits show that the proposed design can reduce the switching activity by 36% to 47% with a negligible effect on the fault coverage.Keywords-low power test, built-in self-test, linear feedback shift register, test pattern generator, weighted switching activity.

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“…In particular, several hybrid BIST schemes store determined top-up patterns ( to detect random pattern resistant faults) on the tester in a reduced form, and then use the existing BIST hardware to attain back these test patterns [6], [7]. Some solutions embed deterministic stimuli by using compressed weights or by disturbing pseudorandom vectors in various fashions [12], [3], [4], [5] .If BIST logic is used to deliver reduced test data, then basic encoding schemes typically take advantage of low fill rates, as originally proposed in LFSR coding , which subsequently developed first into static LFSR reseeding [10],[15], [16] and then into dynamic LFSR reseeding [2]. In the process of conventional scan-based test, hybrid schemes, due to the high data activity associated with scan based test operations, may consume more power than a circuit under-test was designed to function under.…”

Section: Introductionmentioning

confidence: 99%

Design of Reconfigurable Pseudorandom Test Pattern Generator for BSIT

2018

IJRTER

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Abstract:This paper describes a low-power (LP) programmable generator producing pseudorandom test patterns with desired toggling levels and enhanced fault coverage gradient compared with the best-to-date built-in-self-test(BIST)-based pseudorandom test pattern generators. It is comprised of a linear finite state machine driving an appropriate phase shifter, and it comes with a number of features allowing this device to produce binary sequences with preselected toggling (PRESTO) activity. We introduce a method to automatically select several controls of the generator offering easy and precise tuning. State of the development in the semiconductor manufacturing process, integrated chip design methodology, availability of thousand plus pin integrated circuit packaging options and efficient IC test techniques have contributed immensely towards the integration of entire system on a chip. The SystemOn-Chip (SOC) devices can have multiple microprocessors, various types of memories such as SRAM, Flash, Digital Signal Processors, many IP blocks and user defined logics. Numerous SOC test techniques have been innovated in the last decade to test complex mixed signal systems on a chip in a cost effective manner. Test industry has made complete strides in developing new automated test equipment which can analog components, test logic, memory of the chip through external interface to the IC. Here with the experimental results with presence of switching activity in PRESTO, Fully operational PRESTO power comparison is performed with LP Decompressor.

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Bit-swapping LFSR for low-power BIST

Cited by 33 publications

References 2 publications

A low power built in repair analyzer for word oriented memories with optimal repair rate

A low power built in repair analyzer for word oriented memories with optimal repair rate

LT-PRPG: Power minimization technique for test-per-scan BIST

Design of Reconfigurable Pseudorandom Test Pattern Generator for BSIT

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