Bitplane Image Coding With Parallel Coefficient Processing

Aulí-Llinàs, Francesc; Enfedaque, Pablo; Moure, Juan Carlos; Sánchez, Vı́ctor

doi:10.1109/tip.2015.2484069

Cited by 15 publications

(14 citation statements)

References 42 publications

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“…The obtained results hold for different types of images such as those employed in digital cinema, TV production, surveillance, or digital cameras, among others. The performance achieved by BPC-PaCo for different types of images is extensively studied in [20], [21], [24], [26]. Some of the following experiments employ reduced-size versions of these images.…”

Section: Resultsmentioning

confidence: 99%

“…This enormously limits the fine-grained parallelism that can be achieved in highperformance devices such as GPUs. Aimed to tackle this issue, our previous work [20] presented BPC-PaCo, an algorithm that, still employing bitplane strategies and arithmetic coders, divides the workload in small pieces that can be processed by lock-step threads of execution in a SIMD fashion. The proposed method does not sacrifice any of the advanced features of the state-of-the-art coding systems and has only a slight penalization in coding performance.…”

Section: Discussionmentioning

confidence: 99%

“…As described in [20], BPC-PaCo uses three coding passes. We note that the more coding passes employed, the more divergence that occurs in SIMD computing.…”

Section: B Overview Of Compute Unified Device Architecture (Cuda)mentioning

confidence: 99%

“…This is because a finer subdivision of the data improves further the parallelism, helping to hide the execution latencies. Nonetheless, experimental evidence indicates that the coding performance is penalized when using small codeblocks [20]. In general, 64×64 codeblocks provide a good tradeoff between computational and coding performance.…”

Section: A Computational Performance Evaluationmentioning

confidence: 99%

“…Our previous work [20] introduced a bitplane coding engine that unlocks the data dependencies of traditional algorithms. In that work, the proposed bitplane coding with parallel coefficient processing (BPC-PaCo) is introduced in the framework of JPEG2000 without sacrificing any feature of the coding system.…”

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confidence: 99%

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GPU Implementation of Bitplane Coding with Parallel Coefficient Processing for High Performance Image Compression

Enfedaque

Aulí-Llinàs

Moure

2017

IEEE Trans. Parallel Distrib. Syst.

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Abstract-The fast compression of images is a requisite in many applications like TV production, teleconferencing, or digital cinema. Many of the algorithms employed in current image compression standards are inherently sequential. High performance implementations of such algorithms often require specialized hardware like field integrated gate arrays. Graphics Processing Units (GPUs) do not commonly achieve high performance on these algorithms because they do not exhibit fine-grain parallelism. Our previous work introduced a new core algorithm for wavelet-based image coding systems. It is tailored for massive parallel architectures. It is called bitplane coding with parallel coefficient processing (BPC-PaCo). This paper introduces the first high performance, GPU-based implementation of BPC-PaCo. A detailed analysis of the algorithm aids its implementation in the GPU. The main insights behind the proposed codec are an efficient thread-to-data mapping, a smart memory management, and the use of efficient cooperation mechanisms to enable interthread communication. Experimental results indicate that the proposed implementation matches the requirements for high resolution (4K) digital cinema in real time, yielding speedups of 30× with respect to the fastest implementations of current compression standards. Also, a power consumption evaluation shows that our implementation consumes 40× less energy for equivalent performance than state-of-the-art methods.

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Section: Resultsmentioning

confidence: 99%

Section: Discussionmentioning

confidence: 99%

“…As described in [20], BPC-PaCo uses three coding passes. We note that the more coding passes employed, the more divergence that occurs in SIMD computing.…”

Section: B Overview Of Compute Unified Device Architecture (Cuda)mentioning

confidence: 99%

Section: A Computational Performance Evaluationmentioning

confidence: 99%

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confidence: 99%

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