Bitwidth cognizant architecture synthesis of custom hardware accelerators

Mahlke, Scott; Ravindran, Rajiv; Schlansker, Michael; Schreiber, Robert; Sherwood, Timothy

doi:10.1109/43.959864

Cited by 70 publications

(49 citation statements)

References 22 publications

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“…Any out-of-bounds index is silently dropped from considerationhelping designers not to worry about edge cases. A feasible set associated with each hole is computed by static analysis of the index expression similar to classic bitwidth analysis [6].…”

Section: := ??(N); //(1)mentioning

confidence: 99%

SKETCHILOG: Sketching combinational circuits

Becker¹,

Novo²,

Ienne³

2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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Abstract-Despite the progress of higher-level languages and tools, Register Transfer Level (RTL) is still by far the dominant input format for high performance digital designs. Experienced designers can directly express their microarchitectural intuitions in RTL. Yet, RTL is terribly verbose, burdened with trivial details, and thus error prone. In this paper, we augment a modern RTL language (Chisel) with new semantic elements to express an imprecise specification: a sketch. We show how, in combination with a naïve, unoptimized, but functionally correct reference, a designer can utilize the language and supporting infrastructure to focus on the key design intuition and omit some of the necessary details. The resulting design is exactly or almost exactly as good as the one the designer could have achieved by spending the time to manually complete the sketch. We show that, even limiting ourselves to combinational circuits, realistic instances of meaningful design problems are solved quickly, saving considerable design and debugging effort.

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Section: := ??(N); //(1)mentioning

confidence: 99%

SKETCHILOG: Sketching combinational circuits

Becker¹,

Novo²,

Ienne³

2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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“…We used a bit width minimization pass [13] to statically calculate the required bit width of each multiply operation.…”

Section: Multi-pumping Dsps In High-level Synthesismentioning

confidence: 99%

Multi-Pumping for Resource Reduction in FPGA High-Level Synthesis

Canis¹,

Anderson²,

Brown³

2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

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Abstract-Resource sharing is a classic high-level synthesis (HLS) optimization that saves area by mapping multiple operations to a single functional unit. With resource sharing, only operations scheduled in separate cycles can be assigned to shared hardware, which can result in longer schedules. In this paper, we propose a new approach to resource sharing that allows multiple operations to be performed by a single functional unit in one clock cycle. Our approach is based on multi-pumping, which operates functional units at a higher frequency than the surrounding system logic, typically 2×, allowing multiple computations to complete in a single system cycle. Our approach is particularly effective for DSP blocks on an FPGA, which are used to perform multiply and/or accumulate operations. Our results show that resource sharing using multi-pumping is comparable to traditional resource sharing in terms of area saved, but provides significant performance advantages. Specifically, when targeting a 50% reduction in DSP blocks, traditional resource sharing decreases circuit speed performance by 80%, on average, whereas multi-pumping decreases circuit speed by just 5%. Multi-pumping is a viable approach to achieve the area reductions of resource sharing, with considerably less negative impact to circuit performance.

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“…We replace the F distribution function in equation (3) with Gumbel distribution as shown in equation (5).…”

Section: Fig 2 the Gumbel Probability Density Function For Maximum mentioning

confidence: 99%

Stochastic Bit-Width Approximation Using Extreme Value Theory for Customizable Processors

Özer

Nisbet

Gregg

2004

Lecture Notes in Computer Science

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Abstract. Application-specific logic can be generated with a balance and mix of functional units tailored to match an application's computational requirements. The area and power consumption of application-specific functional units, registers and memory blocks is heavily dependent on the bit-widths of operands used in computations. The actual bit-width required to store the values assigned to a variable during execution of a program will not in general match the built-in C data types with fixed sizes of 8, 16, 32 and 64 bits. Thus, precious area is wasted if the built-in data type sizes are used to declare the size of operands. A novel stochastic bit-width approximation technique is introduced to estimate the required bit-width of integer variables using Extreme Value Theory. Results are presented to demonstrate reductions in bit-widths, area and power consumption when the probability of overflow/underflow occurring is varied from 0.1 to infinitesimal levels. Our experimental results show that the stochastic bit-width approximation results in overall 32% reduction in area and overall 21% reduction in the design power consumption on a FPGA chip for nine embedded benchmarks.

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Bitwidth cognizant architecture synthesis of custom hardware accelerators

Cited by 70 publications

References 22 publications

SKETCHILOG: Sketching combinational circuits

SKETCHILOG: Sketching combinational circuits

Multi-Pumping for Resource Reduction in FPGA High-Level Synthesis

Stochastic Bit-Width Approximation Using Extreme Value Theory for Customizable Processors

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