Bitwise scheduling to balance the computational cost of behavioral specifications

Molina, M.C.; Ruiz-Sautua, R.; Mendias, J.M.; Hermida, R.

doi:10.1109/tcad.2005.852663

Cited by 24 publications

(25 citation statements)

References 26 publications

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“…Using proprietary specification formats, and targeting specific applications domain (e.g. DSP) or hardware architecture templates is found in [4], [5], and [6]. High-level synthesis tasks such as the scheduling optimizations have been studied in [1], [7], [8], [9].…”

Section: Related Workmentioning

confidence: 99%

Automatic Generation of Massively Parallel Hardware from Control-Intensive Sequential Programs

Dossis¹

2010

2010 IEEE Computer Society Annual Symposium on VLSI

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Abstract-High-level synthesis has been envisaged as a suitable methodology to design and deliver on time, at least large parts of today's complex IC systems. This paper describes a unified and integrated HLS framework, to automatically produce custom and massively-parallel hardware, including its memory and system interfaces from high-level sequential program code. Using compiler-generators and logic programming techniques, provably-correct hardware compilation flow is achieved. The utilized hardware optimization inference engine is driven by a set of resource constraints, which limit to a certain boundary the number of available hardware operators to function in parallel during each control step. This optimization reduces drastically the number of different control steps (states) of the implemented application. The hardware compilation runs are completed in orders-of-magnitude less time than that which would be needed by even very experienced HDL designers to implement the same applications in RTL code. Implementation results from synthesis of a number of control-dominated, linear and repetitive, applications including a MPEG video compression engine with up to a few hundred states, are presented. In all cases the HLS framework delivers quickly provably-correct, implementable RTL code and the optimized schedule is reduced at up to 30% in comparison with the initial schedule.

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Section: Related Workmentioning

confidence: 99%

Automatic Generation of Massively Parallel Hardware from Control-Intensive Sequential Programs

Dossis¹

2010

2010 IEEE Computer Society Annual Symposium on VLSI

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“…Similar to some aforementioned HLS techniques, fragmentation [16][17][18] would have an indirect impact on power; mainly thanks to the fact that the total effective amount of hardware used at a given clock cycle is reduced. Useless switching activity is produced when executing a narrow operation in a bigger FU.…”

Section: Introductionmentioning

confidence: 99%

“…The goal is to minimize the total amount of hardware used and in this process some wide operations can be divided into fragments such that they can be executed on a narrow width FU. Scheduling techniques have been proposed to accompany fragmentation, where fragments of the same operation could be scheduled in non-consecutive cycles [17,18]. Thereby, a small set of effective FUs would be utilized to the maximum extent across all clock cycles.…”

Section: Introductionmentioning

confidence: 99%

“…Besides, to lessen the abovementioned adverse impacts of existing fragmentation-based flows on power we propose a different scheduling approach to comply with the original latency constraint of the homogenous datapath. We start out by utilizing the main principle of fragmentation as a tool for minimizing hardware used per cycle [18]. However, instead of scheduling several fragments of the same operation in different control steps (csteps), as practiced by prior techniques [17,18], FUs are fragmented, but operations are executed in a set of linked FUs in the csteps when they were originally scheduled [16].…”

Section: Introductionmentioning

confidence: 99%

“…We start out by utilizing the main principle of fragmentation as a tool for minimizing hardware used per cycle [18]. However, instead of scheduling several fragments of the same operation in different control steps (csteps), as practiced by prior techniques [17,18], FUs are fragmented, but operations are executed in a set of linked FUs in the csteps when they were originally scheduled [16]. In this way we keep a similar execution time to the common case, which combined with the power reduction will produce an overall energy decrease.…”

Section: Introductionmentioning

confidence: 99%

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Power optimization in heterogenous datapaths

Barrio

Memik

Molina

et al. 2011

2011 Design, Automation &Amp; Test in Europe

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12 -Heterogenous datapaths maximize the utilization of functional units (FUs) by customizing their widths individually through fragmentation of wide operands. In comparison, slices in large functional units in a homogenous datapath could be spending many cycles not performing actual useful work. Various fragmentation techniques demonstrated benefits in minimizing the total functional unit area. Upon a closer look at fragmentation techniques, we observe that the area savings achieved by heterogenous datapaths can be traded-off for power optimization. Our specific approach is to introduce choices for functional units with power/area trade-offs for different fragmentation and allocation choices, for reducing power consumption while satisfying the area constraint imposed on the heterogenous datapath. As low power FUs in literature produce an area penalty, a methodology must be developed in order to introduce them in the HLS flow while complying with the area constraint. We propose an allocation and module selection algorithms that pursue a trade-off between area and power consumption for fragmented datapaths under a total area constraint. Results show that it is possible to reduce power by 37% on average (49% in the best case). Moreover latency and cycle time will be equal or nearly the same as in the baseline case, which will lead to an energy reduction, too.

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