Black border, mask 3D effects: covering challenges of EUV mask architecture for 22nm node and beyond

Davydova, Natalia; Setten, Eelco van; Kruif, Robert de; Connolly, Brid; Fukugami, Norihito; Kodera, Yutaka; Morimoto, Hiroaki; Sakata, Yo; Kotani, Jun; Kondo, Shinpei; Imoto, Tomohiro; Rolff, Haiko; Ullrich, Albrecht; Jaganatharaja, Ramasubramanian Kottumakulal; Lammers, Ad; Oorschot, Dorothe; Man, Cheuk-Wah; Schiffelers, Guido; Dijk, Joep van

doi:10.1117/12.2066299

Cited by 7 publications

(3 citation statements)

References 3 publications

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“…We start with the black border edge placement accuracy and estimating the safe distance to the black border edge. At ASML only one black border type is used: etched multilayer black border [4], [5], [6]. The black border edge placement accuracy was evaluated on state-of-the-art masks (Figure 6, courtesy of DNP).…”

Section: Black Border Edge Position Accuracymentioning

confidence: 99%

Overview of stitching for high NA: imaging and overlay experimental and simulation results

Davydova¹,

Look²,

Wiaux³

et al. 2023

Optical and EUV Nanolithography XXXVI

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An increased interest to stitching for High NA EUVL is observed; this is driven by expected higher demand of larger size chips for various applications. In the past a recommendation was published [1] to have 1-5 um band where no critical structures of a High NA layer would be allowed. In [2], we have introduced new insights on at-resolution stitching. In this publication, we present new experimental results obtained on NXE:3400B scanner. In the past we showed NXE feasibility results of vertical lines and contact holes stitching at relaxed resolution (40-48 nm pitch) in a single wafer location. In this study we evaluate stitching behavior through slit at more aggressive resolutions (P36 and P24 lines / spaces).We provide an overview of interactions in the stitching area such as aerial image interactions, absorber reflection, absorber to black border transition, black border vicinity impact and show corresponding experimental and simulations results. We formulate initial requirements for black border edge placement control and show performance of new masks. For stitching with low-n masks, we discuss using sub-resolution gratings to suppress the elevated mask reflectivity. We show rigorous simulations of stitched images, its sensitivity to overlay errors and propose mitigation mechanisms for OPC. Finally, an overview of stitching enablers will be described: from improved reticle black border position accuracy and absorber reflectivity control to mask resolution and OPC requirements.

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Section: Black Border Edge Position Accuracymentioning

confidence: 99%

Overview of stitching for high NA: imaging and overlay experimental and simulation results

Davydova¹,

Look²,

Wiaux³

et al. 2023

Optical and EUV Nanolithography XXXVI

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show abstract

“…With advanced design nodes below 45 nm the mask 3D effects have become more pronounced. It is observed that in dense structure regions using oblique illumination and an attenuated phase shifting mask (att-PSM), the intensity of zero-and first-order diffraction changes as pitch shrinks [33][34][35][36].…”

Section: Phase Shift Maskmentioning

confidence: 99%

Lithography technology for advanced devices and introduction to integrated CAD analysis for hotspot detection

Vikram

Agarwal

2017

IET Circuits, Devices & Systems

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Optical projection lithography has been the workhorse of the integrate circuit (IC) manufacturing industry to transfer the computer-aided design (CAD) to semiconducting material wafers. The resolution limit of the 193 nm wavelength lithography which was initially targeted for the 90 nm design rule has been further extended to realise ∼10-20 nm devices with ingenious interventions. The three-dimensional fin-shaped field-effect transistor device structure now realise the <20 nm design rule still using 193 nm projection lithography as the widely accepted solution. The extreme ultraviolet wavelength source systems are still in development and testing phases with some recent success reported, but still falling short of supporting volume production requirements. This study reviews the current trends in lithography and the associated resolution enhancement techniques with brief introduction to an integrated CAD analysis for hotspot detection.

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“…It is observed that in dense structure regions using oblique illumination and an attenuated phase shifting mask (att-PSM), the intensity of zero and first order diffraction changes as pitch shrinks [33][34][35][36].…”

Section: Phase Shift Maskmentioning

confidence: 99%

Critical Review of Current Trends in ASIC Writing and Layout Analysis

Vikram¹,

Agarwal

2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Electrical Designs for Application SpecificIntegrated Circuits (ASIC) has undergone a change recently with the advent of the sub-wavelength lithography. The optical projection with 193 nm wavelength has been further extended with the use of immersion and other techniques. The competing trends for printing smaller design features have been discussed in this paper with the discussion of the electrical layout analysis to find unfriendly design features. The early knowledge of the unfriendly design features allows remedial actions in time for better yield on the wafer. There are existing standard design qualification criteria being used in the design and fabrication community, but they seem to be insufficient to guarantee defect free designs. This paper proposes an integrated approach for screening the layout with multiple aspects: layout geometry based, graphical analysis and process model based verification. The results have been discussed with few example design features from the 28nm design layout.

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Black border, mask 3D effects: covering challenges of EUV mask architecture for 22nm node and beyond

Cited by 7 publications

References 3 publications

Overview of stitching for high NA: imaging and overlay experimental and simulation results

Overview of stitching for high NA: imaging and overlay experimental and simulation results

Lithography technology for advanced devices and introduction to integrated CAD analysis for hotspot detection

Critical Review of Current Trends in ASIC Writing and Layout Analysis

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