Body Biased Sense Amplifier With Auto-Offset Mitigation for Low-Voltage SRAMs

Patel, Dhruv; Neale, Adam; Wright, Derek; Sachdev, Manoj

doi:10.1109/tcsi.2021.3081917

Cited by 13 publications

(11 citation statements)

References 48 publications

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“…Transistors P1, P2, N2, and N3 form a current conveyor as a column sector, as in Figure 10 . When the Bit signal is low while the cell is accessed for turning ON the transistors M2 and N3, the differential signal will flow from the bitlines to the data lines [ 1 ]. From the perspective of a circuit that operates in voltage mode, P1, P2, and N2, N3 build up two MOS amplifiers.…”

Section: Design and Implementation Of Sense Amplifier Schemesmentioning

confidence: 99%

“…In the previous study, it was believed that nodes had equivalent voltages. [ 1 ]. This 6T-SRAM circuit is designed using CMOS inverters.…”

Section: Design and Implementation Of Sense Amplifier Schemesmentioning

confidence: 99%

“…As only a single row of content is accessible per read cycle, each SRAM column needs only one sense amplifier. Integrating differential logic networks reduces their complexity and average delay [ 1 , 2 , 3 ]. Modeling high-speed sense amplifiers is difficult since each generation of complementary metal-oxide semiconductor SRAMs reduces memory cell size by one-third and increases chip size by 1.5 times, increasing power consumption.…”

Section: Introductionmentioning

confidence: 99%

“…The Differential-Input Body Biased Sense Amplifier (DIBBSA) is designed with au-to-offset mitigation for low-voltage SRAMs, and differential bitline signals are fed to the source and body of the critical sensing transistors [ 1 ]. In 65-nm CMOS technology with various operational modes, the usefulness of body biasing in lowering offset is examined.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Novel Low Power Cross-Coupled FET-Based Sense Amplifier Design for High-Speed SRAM Circuits

et al. 2023

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We live in a technologically advanced society where we all use semiconductor chips in the majority of our gadgets, and the basic criterion concerning data storage and memory is a small footprint and low power consumption. SRAM is a very important part of this and can be used to meet all the above criteria. In this study, LTSpice software is used to come up with a high-performance sense amplifier circuit for low-power SRAM applications. Throughout this research, various power reduction approaches were explored, and the optimal solution has been implemented in our own modified SRAM design. In this article, the effect of power consumption and the reaction time of the suggested sense amplifier were also examined by adjusting the width-to-length (W/L) ratio of the transistor, the power supply, and the nanoscale technology. The exact amount of power used and the number of transistors required by different approaches to better comprehend the ideal technique are also provided. Our proposed design of a low-power sense amplifier has shown promising results, and we employ three variations of VLSI power reduction techniques to improve efficiency. Low-power SRAMs embrace the future of memory-centric neuromorphic computing applications.

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Section: Design and Implementation Of Sense Amplifier Schemesmentioning

confidence: 99%

“…In the previous study, it was believed that nodes had equivalent voltages. [ 1 ]. This 6T-SRAM circuit is designed using CMOS inverters.…”

Section: Design and Implementation Of Sense Amplifier Schemesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Novel Low Power Cross-Coupled FET-Based Sense Amplifier Design for High-Speed SRAM Circuits

et al. 2023

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show abstract

“…Recently, numerous VLSA [15], [16], [17], [18], [19], [31], CLSA [20], [21], [22], [23], [24], [25], [26], [27], and hybrid latch type SA [28], [29] designs have been proposed to mitigate coupling effect [18], power consumption [26], [27], and V OS problem [15], [16], [17], [20], [21], [22], [23], [24], [25], [28], [29], [31]. Among the V OS related previous works, a few of them suggested utilizing an external circuit after fabrication for V OS calibration to minimize the V OS [23], [24] and most of them proposed internal circuit design modifications to minimize the V OS [15], [16], [17], [20], [21], [22], [25], [28], [29], [31]. In particular, Singh et al [19] reported a V OS reduction technique by controlling the rise time (T RISE ) of the SAE signal in VLSAs.…”

Section: Introductionmentioning

confidence: 99%

Offset-Canceling Current-Latched Sense Amplifier With Slow Rise Time Control and Reference Voltage Biasing Techniques

Ishdorj

Kim

Ahn

et al. 2023

IEEE Trans. Circuits Syst. I

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The current-latched sense amplifier (CLSA) is a promising candidate for detecting stored values in a memory cell. With technology shrinks, however, the input referred offset voltage (V OS ) in the SA increases, resulting in a degradation of the memory read yield. To obtain a high read yield, V OS reduction and cancellation techniques have become essential in deep-submicrometer technology nodes. When determining the V OS in the CLSA, the voltage mismatch of the input NMOS pair is the dominant factor (∼75%), followed by that of the latch NMOS pair (∼25%). In this paper, 1) slow rise time (T RISE ) control technique of SA enable signal and 2) reference voltage (V REF ) biasing technique are proposed, and the effectiveness of the proposed techniques are analyzed for the conventional CLSA with footswitch (FS-CLSA) and offset-canceling CLSA (OC-CLSA). Post-layout based HSPICE simulation results using 28 nm model parameters show that the FS-CLSA with size-up strategy (OC-CLSA) achieves a 17.7% (10.5%) reduction of the standard deviation of V OS (σ OS ) when a slow T RISE of 0.6 ns is employed. The measurement results from a 28 nm test chip show that the OC-CLSA with V REF biasing achieves a 22% reduction of σ OS compared to the conventional OC-CLSA.Index Terms-Current-latched sense amplifier (CLSA), offsetcanceling CLSA (OC-CLSA), offset voltage, read yield, reference voltage (V REF ) biasing, slow rise time (T RISE ) of SA enable signal, threshold voltage (V TH ) mismatch.

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Real‐time bit‐line leakage balance circuit with four‐input low‐offset SA considering threshold voltage for SRAM stability design

Peng,

Hu,

Zheng

et al. 2024

Circuit Theory & Apps

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In an SRAM, threshold voltages of transistors decrease as the CMOS process technology scales down into the nanometer scale, which causes the leakage currents on the bit‐lines. The bit‐line leakage current slows reading operations or even causes reading errors. In this paper, we proposed a new scheme called RTB, which is combined with a four‐input low‐offset sense amplifier with threshold voltage consideration to solve the problem caused by bit‐line leakage current. This scheme adopts 8T cells and two pairs of bit‐lines connected to a four‐input sense amplifier to balance the bit‐line leakage current in real‐time. In this way, the maximum tolerable bit‐line leakage current can be effectively increased and the reading operation can be accelerated. Simulations in the 55 nm CMOS process design kits under different process corners, temperatures, and voltages show that the proposed scheme can increase the maximum tolerable leakage to more than 300 μA.

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Body Biased Sense Amplifier With Auto-Offset Mitigation for Low-Voltage SRAMs

Cited by 13 publications

References 48 publications

Novel Low Power Cross-Coupled FET-Based Sense Amplifier Design for High-Speed SRAM Circuits

Novel Low Power Cross-Coupled FET-Based Sense Amplifier Design for High-Speed SRAM Circuits

Offset-Canceling Current-Latched Sense Amplifier With Slow Rise Time Control and Reference Voltage Biasing Techniques

Real‐time bit‐line leakage balance circuit with four‐input low‐offset SA considering threshold voltage for SRAM stability design

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