2016 Euromicro Conference on Digital System Design (DSD) 2016
DOI: 10.1109/dsd.2016.35
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Boolean Difference Based Reliability Evaluation of Fault-Tolerant Circuit Structures on FPGAs

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(2 citation statements)
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“…(i) e mathematical models of these schemes are mature and have been analyzed in the literature [40,41] (ii) e probabilistic schemes are able to comprehend very small differences in reliability among slightly different redundant structures Among the probabilistic computational reliability schemes, we decided to use the Boolean Difference Error Calculator (BDEC) method based on the analysis and merits/demerits of various computation schemes explained in our previous work [40][41][42]. e basic BDEC model was, however, limited as it did not cover sequential circuits and could not deal with redundant circuit structures.…”
Section: Replication Via the Banl Tmr Toolmentioning
confidence: 99%
See 1 more Smart Citation
“…(i) e mathematical models of these schemes are mature and have been analyzed in the literature [40,41] (ii) e probabilistic schemes are able to comprehend very small differences in reliability among slightly different redundant structures Among the probabilistic computational reliability schemes, we decided to use the Boolean Difference Error Calculator (BDEC) method based on the analysis and merits/demerits of various computation schemes explained in our previous work [40][41][42]. e basic BDEC model was, however, limited as it did not cover sequential circuits and could not deal with redundant circuit structures.…”
Section: Replication Via the Banl Tmr Toolmentioning
confidence: 99%
“…e experimental data used to support the findings of this study are included within the articleas well as in authors' previous research works [40][41][42][48][49][50].…”
Section: Data Availabilitymentioning
confidence: 99%