Boosting the performance of shared memory multiprocessors

Stenström, Per; Brorsson, Mats; Dahlgren, Fredrik; Grahn, Håkan; Dubois, Michel

doi:10.1109/2.596630

Cited by 9 publications

(4 citation statements)

References 17 publications

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“…Some hardware optimizations, proposed to shorten the time processors loose because of cache misses and invalidations, were evaluated in [14]. In [15], the remote memory access latency is reduced by placing caches in the crossbar switches of the interconnect to capture and store shared data as they flow from the memory module to the requesting processor.…”

Section: Related Workmentioning

confidence: 99%

An architecture for high-performance scalable shared-memory multiprocessors exploiting on-chip integration

Acacio

González

García

et al. 2004

IEEE Trans. Parallel Distrib. Syst.

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Abstract-Recent technology improvements allow multiprocessor designers to put some key components inside the processor chip, such as the memory controller, the coherence hardware, and the network interface/router. In this paper, we exploit such integration scale, presenting a novel node architecture aimed at reducing the long L2 miss latencies and the memory overhead of using directories that characterize cc-NUMA machines and limit their scalability. Our proposal replaces the traditional directory with a novel three-level directory architecture, as well as it adds a small shared data cache to each of the nodes of a multiprocessor system. Due to their small size, the first-level directory and the shared data cache are integrated into the processor chip in every node, which enhances performance by saving accesses to the slower main memory. Scalability is guaranteed by having the second and third-level directories out of the processor chip and using compressed data structures. A taxonomy of the L2 misses, according to the actions performed by the directory to satisfy them, is also presented. Using execution-driven simulations, we show that significant latency reductions can be obtained by using the proposed node architecture, which translates into reductions of more than 30 percent in several cases in the application execution time.Index Terms-cc-NUMA multiprocessor, directory memory overhead, L2 miss latency, three-level directory, shared data cache, onprocessor-chip integration.

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Section: Related Workmentioning

confidence: 99%

An architecture for high-performance scalable shared-memory multiprocessors exploiting on-chip integration

Acacio

González

García

et al. 2004

IEEE Trans. Parallel Distrib. Syst.

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“…Based on prerequisites from a course in parallel computer architecture, the students have studied memory system optimization techniques such as cache coherence protocol enhancements [7] and selected promising candidates based on application/architecture interactions.…”

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confidence: 99%

A holistic approach to computer system design education based on system simulation techniques

Stenström

Dahlgren

1998

Proceedings of the 1998 Workshop on Computer Architecture Education - WCAE '98

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In the design of competitive application-specific computer systems, it is important to evaluate design alternatives in which commodity hardware and software components are interwoven with tailor-made components. At Chalmers, we are offering a specialization in computer engineering that emphasizes a holistic approach to the design of application-specific computer systems. Apart from offering disciplinary courses in hardware and software technologies, and design methods, it also offers a project course in which the students apply a holistic design methodology to realistic system design projects. A key component in this project course is the use of system simulation techniques, that have been developed in computer architecture research projects, as an important infrastructure to attack design issues spanning all design levels. This paper provides an overview of the educational goals and the course content of the specialization. It then discusses how system simulation techniques have been used in the project course. IntroductionA prevailing methodology in the design of computer systems is to carefully analyze the interaction between the application and a computer-system design alternative with respect to e.g. performance consequences. While this methodology has been applied to the design of instruction-set architectures (ISAs) for several decades, it is applicable to the design of almost any component of contemporary computer systems such as compilers, operating systems, memory and I/O subsystems. This design methodology now forms a common ground for computer architecture courses thanks to the widely adopted text by Hennessy and Patterson [2]. While this textbook mainly focuses on how the methodology is applied to the design of microprocessors, it can be naturally generalized to the design of application-specific computer systems, where commodity components (microprocessors and standard software packages) are interwoven with tailor-made components. Training engineers to make design tradeoffs in a systematic way is an important goal for computer-engineering curricula in Sweden as well as elsewhere.At Chalmers, a computer-system design specialization within the computer science and engineering curriculum has been designed that has this educational goal in mind. In this paper, we discuss our strategy to reach this goal. In particular, we present our ideas of a project course in which a holistic approach is taken to analyze and compare design alternatives of application-oriented computer systems. In Section 2.0, we discuss the overall educational goals of the specialization in more detail. Section 3.0 then focuses on the content in terms of courses and how they together meet the goal. One such course is a computer-system project course that aims at providing a holistic view of computer-system design and in which all the other disciplinary courses are put into perspective. In Section 4.0 we finally present how we use system simulation techniques in this project course as an important infrastructure to apply a hol...

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“…Some hardware optimizations, proposed to shorten the time processors loose because of cache misses and invalidations, were evaluated in [18]. More recently, in [9], [10] and [14], coherence messages are predicted and in [11], prediction-based self-invalidation techniques are applied to reduce the coherence overhead.…”

Section: Related Workmentioning

confidence: 99%

Reducing the latency of L2 misses in shared-memory multiprocessors through on-chip directory integration

Acacio

González

García

et al.

Proceedings 10th Euromicro Workshop on Parallel, Distributed and Network-Based Processing

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Boosting the performance of shared memory multiprocessors

Cited by 9 publications

References 17 publications

An architecture for high-performance scalable shared-memory multiprocessors exploiting on-chip integration

An architecture for high-performance scalable shared-memory multiprocessors exploiting on-chip integration

A holistic approach to computer system design education based on system simulation techniques

Reducing the latency of L2 misses in shared-memory multiprocessors through on-chip directory integration

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