Border Trap Extraction with Capacitance- Equivalent Thickness to Reflect the Quantum Mechanical Effect on Atomic Layer Deposition High-k/In0.53Ga0.47As on 300-mm Si Substrate

Abstract

This study presents a model to calculate the border trap density (N bt ) of atomic layer deposition high- k onto In 0.53 Ga 0.47 As on a 300-mm (001) Si substrate. This model considers the quantum confinement effect and band nonparabolicity. Capacitance-equivalent thickness (CET) was used to reflect the distance of the charge centroid from the oxide–semiconductor interface. The border trap values based on CET were found to be approximately 65% lower than the extracted values based on physical thickness in the In 0.53 Ga 0.47 As material. In an investigation of two different post-metal annealing effects on border traps, the border trap was more effectively passivated by N 2 -based forming gas annealing (FGA) compared with rapid thermal annealing (RTA), whereas a lower interface state density was observed in RTA-annealed samples compared with FGA-annealed samples. N bt extraction at different bias voltages demonstrated that the applied frequencies travel deep into the oxide and interact with more traps as more the Fermi level passes the conduction band, thus creating tunneling with the carriers.

Border Trap Characterizations of Al2O3/ZrO2 and Al2O3/HfO2 Bilayer Films Based on Ambient Post Metal Annealing and Constant Voltage Stress

“…Then, the substrate was dried in a nitrogen(N 2 ) environment for the prevention of water mask formation on the surface and transferred to the ALD chamber ("Atomic Classic", CN1, Gyenggi-do, Korea) within a minimal time interval. Before the actual film deposition, the substrates were pretreated with 10 cycles of TMA pulses to passivate the surface due to its' "self-cleaning effect" [10]. Then, two individual depositions of Al 2 O 3 /ZrO 2 (1 nm/3.3 nm) and Al 2 O 3 /HfO 2 (1 nm/3 nm) were performed followed by ALD TiN (5 nm) deposition on the top of the oxide layer.…”

“…In addition, these materials have already been developed in defense and high-frequency analog applications [8,9]. The high velocities are attained by reimbursing a lower effective mass which causes the "density of state bottleneck" dilemma which pins the fermi level, E F , inside the conduction band, resulting in a reduction of the conduction band distinction height [9][10][11]. This disposition of the fermi level makes itself align with the border trap's energy levels, which are located near the interfacial oxide region with the semiconductor inside the oxide [10,12].…”

“…The high velocities are attained by reimbursing a lower effective mass which causes the "density of state bottleneck" dilemma which pins the fermi level, E F , inside the conduction band, resulting in a reduction of the conduction band distinction height [9][10][11]. This disposition of the fermi level makes itself align with the border trap's energy levels, which are located near the interfacial oxide region with the semiconductor inside the oxide [10,12]. When an AC signal is superimposed with the applied DC bias, there is a tunneling of channel electrons into or emitting between the border traps and the semiconductor.…”

“…Usually, these near interfacial traps are categorized by their position inside the oxide; the furthermost trap takes the longest time to fill. So this charge exchange time is characterized by the depth of the traps inside the oxide which also depends on the applied frequency [10,13]. This creates a frequency dependent capacitance response in the accumulation and these traps are also responsible for dilapidation of mobility, on-state current, transconductance, and reliability by causing high hysteresis, threshold voltage instability, and phonon scattering [10][11][12]14].…”

“…So this charge exchange time is characterized by the depth of the traps inside the oxide which also depends on the applied frequency [10,13]. This creates a frequency dependent capacitance response in the accumulation and these traps are also responsible for dilapidation of mobility, on-state current, transconductance, and reliability by causing high hysteresis, threshold voltage instability, and phonon scattering [10][11][12]14]. Moreover, as a reliability issue, it has already been reported that the constant-voltage-stress (CVS) is responsible for electron trapping in these acceptors like oxide traps as well as the creation of new oxygen vacancy defects [8,15,16].…”