Fully depleted silicon on insulator (FD-SOI) MOSFET using low temperature sputtering SiO2 gate insulator (GI) was fabricated with resistless process without cleanroom and showed a characteristic comparable to that using plasma enhanced CVD. Resultant average characteristics with standard deviations were, field effect mobility µn of 612±37 cm2/Vs and subthreshold swing ss of 135±18 mV/dec. These were compared with our previous single crystal thin-film transistors (TFTs) on glass substrate with µn of 339±116 cm2/Vs and ss of 255±24 mV/dec, and it was cleared that inferior ss in TFTs was originated from bad bottom Si/SiO2 interface quality with a trap density of 1×1012 cm-2V-1. It was also shown that to achieve TFT characteristics the same as the FD-SOI-MOSFET, top interface trap density and bottom interface quality had better lower than 1×1011 cm-2V-1.