Bottom-Up Approach for High Speed SRAM Word-line Buffer Insertion Optimization

Abstract

The delay of a square SRAM array is dominated by the bit line delay due to the high capacitance per unit length attached to the bit line. Hence, SRAM arrays are usually longer in the word line direction. However, the word line delay also increases dramatically in a simple naive topology and can be a dominating factor when the word line dimension is much longer than that of the bit line. Therefore, word line optimization is an important part of SRAM delay optimization. Buffer insertion, which is commonly used for long interconnects, can also be used to improve word line delay. This paper proposes an approach to place and size the buffers to reduce word line and overall SRAM delay. The proposed methodology improves the read critical path delay by 15.7%, at the cost of only 5.26% extra area in a 128 Kbit SRAM.

Design and Analysis of Negative Capacitance Assisted SRAM: A Compact Model Based Study

“…Also, in the system with multiple loads in a long wire, coupling capacitance, especially the WL rising transition and the precharge signal lowering transition, can have a considerable effect on SRAM bit cell performance [10]. This is because the resistance and coupling capacitance of WL wire formed the resistor-capacitance (RC) network at the WL's signal [11]. This results in non-scaling RC with scaling [12], which is unacceptable in a high-performance SRAM design.…”