Bounded depth circuits with weighted symmetric gates: Satisfiability, lower bounds and compression

Sakai, Takayuki; Seto, Kazuto; Tamaki, Suguru; Teruyama, Junichi

doi:10.1016/j.jcss.2019.04.004

Cited by 5 publications

(10 citation statements)

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“…Since every k-PTF f can be sign-represented by an integer polynomial with coefficients of size 2 poly(m) [17], this can be done with a table of size 2 poly(m) and in time 2 poly(m) . When the coefficients are small (say of bit-complexity ≤ n o (1) ), then this strategy already yields a #SAT algorithm, as observed by Sakai et al [22]. Unfortunately, in general, given a restriction…”

Section: Satisfiability Algorithm For K-ptfsmentioning

confidence: 92%

“…An incomparable result was proved by Williams [29] who obtained algorithms for subexponential-sized circuits from the class ACC 0 • LTF, which is a subclass of subexponential TC 0 . 9 For the special case of k-PTFs (and generalizations to sparse PTFs over the {0, 1} basis) with small weights, a #SAT algorithm was devised by Sakai et al [22]. 10 The high-level idea of our algorithm is the same as theirs.…”

Section: Outputmentioning

confidence: 99%

“…Hence, it is not clear if the class of subexponential-sized ACC 0 • LTF circuits contains even depth-2 TC 0 circuits of linear size. 10 More specifically, the algorithm of Sakai et al [22] works as long as the weight of the input polynomial…”

Section: Outputmentioning

confidence: 99%

“…At a high level, we follow the same strategy as Sakai et al [22]. Their algorithm uses memoization, which is a standard and very useful strategy for satisfiability algorithms (see, e.g.…”

Section: Satisfiability Algorithm For K-ptfsmentioning

confidence: 99%

“…This intuition was provided to us by Ryan Williams 5. An algorithm was claimed for this problem in the work of Sakai, Seto, Tamaki and Teruyama[22].Unfortunately, the proof of this claim only works when the weights are suitably small. See Footnote 1 on page 4 of[14].…”

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confidence: 99%

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A #SAT Algorithm for Small Constant-Depth Circuits with PTF gates

et al. 2022

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We show that there is a zero-error randomized algorithm that, when given a small constantdepth Boolean circuit C made up of gates that compute constant-degree Polynomial Threshold functions or PTFs (i.e., Boolean functions that compute signs of constant-degree polynomials), counts the number of satisfying assignments to C in significantly better than brute-force time.Formally, for any constants d, k, there is an ε > 0 such that the zero-error randomized algorithm counts the number of satisfying assignments to a given depth-d circuit C made up of k-PTF gates such that C has size at most n 1+ε . The algorithm runs in time 2 n−n Ω(ε) .Before our result, no algorithm for beating brute-force search was known for counting the number of satisfying assignments even for a single degree-k PTF (which is a depth-1 circuit of linear size).The main new tool is the use of a learning algorithm for learning degree-1 PTFs (or Linear Threshold Functions) using comparison queries due to Kane, Lovett, Moran and Zhang (FOCS 2017). We show that their ideas fit nicely into a memoization approach that yields the #SAT algorithms.

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Section: Satisfiability Algorithm For K-ptfsmentioning

confidence: 92%

Section: Outputmentioning

confidence: 99%

Section: Outputmentioning

confidence: 99%

“…At a high level, we follow the same strategy as Sakai et al [22]. Their algorithm uses memoization, which is a standard and very useful strategy for satisfiability algorithms (see, e.g.…”

Section: Satisfiability Algorithm For K-ptfsmentioning

confidence: 99%

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confidence: 99%

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A #SAT Algorithm for Small Constant-Depth Circuits with PTF gates

et al. 2022

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Fooling Constant-Depth Threshold Circuits (Extended Abstract)

Hatami

Hoza

Tal

et al. 2022

2021 IEEE 62nd Annual Symposium on Foundations of Computer Science (FOCS)

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Quantified derandomization of linear threshold circuits

Tell

2018

Proceedings of the 50th Annual ACM SIGACT Symposium on Theory of Computing

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One of the prominent current challenges in complexity theory is the attempt to prove lower bounds for T C 0 , the class of constant-depth, polynomial-size circuits with majority gates. Relying on the results of Williams (2013), an appealing approach to prove such lower bounds is to construct a non-trivial derandomization algorithm for T C 0 . In this work we take a first step towards the latter goal, by proving the first positive results regarding the derandomization of T C 0 circuits of depth d > 2.Our first main result is a quantified derandomization algorithm for T C 0 circuits with a super-linear number of wires. Specifically, we construct an algorithm that gets as input a T C 0 circuit C over n input bits with depth d and n 1+exp(−d) wires, runs in almostpolynomial-time, and distinguishes between the case that C rejects at most 2 n 1−1/5d inputs and the case that C accepts at most 2 n 1−1/5d inputs. In fact, our algorithm works even when the circuit C is a linear threshold circuit, rather than just a T C 0 circuit (i.e., C is a circuit with linear threshold gates, which are stronger than majority gates).Our second main result is that even a modest improvement of our quantified derandomization algorithm would yield a non-trivial algorithm for standard derandomization of all of T C 0 , and would consequently imply that N E X P ⊆ T C 0 . Specifically, if there exists a quantified derandomization algorithm that gets as input a T C 0 circuit with depth d and n 1+O(1/d) wires (rather than n 1+exp(−d) wires), runs in time at most 2 n exp(−d) , and distinguishes between the case that C rejects at most 2 n 1−1/5d inputs and the case that C accepts at most 2 n 1−1/5d inputs, then there exists an algorithm with running time 2 n 1−Ω(1) for standard derandomization of T C 0 . 7 Quantified derandomization of depth-2 linear threshold circuits 35 8 Restrictions for sparse T C 0 circuits: A potential path towards N E X P ⊆ T C 0 38 Acknowledgements 38 Appendix A Quantified derandomization and lower bounds 43 Appendix B Proof of a technical claim from Section 6 44 i 1. The circuit C mapsn input bits ton =n · (1/ǫ) O(1/ρ) output bits.

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Bounded depth circuits with weighted symmetric gates: Satisfiability, lower bounds and compression

Cited by 5 publications

References 58 publications

A #SAT Algorithm for Small Constant-Depth Circuits with PTF gates

A #SAT Algorithm for Small Constant-Depth Circuits with PTF gates

Fooling Constant-Depth Threshold Circuits (Extended Abstract)

Quantified derandomization of linear threshold circuits

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