Bounding Worst-Case Performance for Multi-Core Processors with Shared L2 Instruction Caches

Yan, Jun; Zhang, Wei

doi:10.5626/jcse.2011.5.1.001

Cited by 3 publications

(4 citation statements)

References 34 publications

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“…Therefore, it becomes increasingly important to design an efficient and scalable timing analysis method to safely and accurately estimate the WCET for hard real-time tasks running on multicore processors with shared resources. While there have been several research efforts on multicore timing analysis [1][2][3][4]6], they have either been limited to instruction caches only, or have significant computation cost that is not scalable.…”

Section: Discussionmentioning

confidence: 99%

“…Multicore WCET analysis has been actively investigated recently. Yan and Zhang [1,2] proposed a coarsegrain approach to calculate the WCET of multicore processors with shared instruction caches. The worst-case inter-thread cache interferences and the WCET were cal-culated by an extended integer linear programming (ILP) approach, which modeled all the possible inter-thread cache conflicts [3].…”

Section: Introductionmentioning

confidence: 99%

“…The worst-case inter-thread cache interferences and the WCET were cal-culated by an extended integer linear programming (ILP) approach, which modeled all the possible inter-thread cache conflicts [3]. While these two approaches [1][2][3] are safe, they may lead to overestimation of the WCET, because both approaches compute the worst-case instruction cache performance and the worst-case path separately. Also, these two approaches are limited to directedmapped instruction caches only, which do not support timing analysis of set-associative caches or data caches in their current forms.…”

Section: Introductionmentioning

confidence: 99%

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Counter-Based Approaches for Efficient WCET Analysis of Multicore Processors with Shared Caches

Ding

Zhang

2013

Journal of Computing Science and Engineering

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To enable hard real-time systems to take advantage of multicore processors, it is crucial to obtain the worst-case execution time (WCET) for programs running on multicore processors. However, this is challenging and complicated due to the inter-thread interferences from the shared resources in a multicore processor. Recent research used the combined cache conflict graph (CCCG) to model and compute the worst-case inter-thread interferences on a shared L2 cache in a multicore processor, which is called the CCCG-based approach in this paper. Although it can compute the WCET safely and accurately, its computational complexity is exponential and prohibitive for a large number of cores. In this paper, we propose three counter-based approaches to significantly reduce the complexity of the multicore WCET analysis, while achieving absolute safety with tightness close to the CCCG-based approach. The basic counter-based approach simply counts the worst-case number of cache line blocks mapped to a cache set of a shared L2 cache from all the concurrent threads, and compares it with the associativity of the cache set to compute the worst-case cache behavior. The enhanced counter-based approach uses techniques to enhance the accuracy of calculating the counters. The hybrid counter-based approach combines the enhanced counter-based approach and the CCCG-based approach to further improve the tightness of analysis without significantly increasing the complexity. Our experiments on a 4-core processor indicate that the enhanced counter-based approach overestimates the WCET by 14% on average compared to the CCCG-based approach, while its averaged running time is less than 1/380 that of the CCCG-based approach. The hybrid approach reduces the overestimation to only 2.65%, while its running time is less than 1/150 that of the CCCG-based approach on average.

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Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Counter-Based Approaches for Efficient WCET Analysis of Multicore Processors with Shared Caches

Ding

Zhang

2013

Journal of Computing Science and Engineering

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“…In [6], recent theoretical results for dynamic power management of multi-core processors were summarized. In [7] and [8], methods to estimate the worst-case execution time of applications running on multi-core processors were proposed.…”

Section: Related Workmentioning

confidence: 99%

A Technique for Fast Process Creation Based on Creation Location

Kim¹,

Ahn²,

Chung³

2011

Journal of Computing Science and Engineering

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Due to the proliferation of software parallelization on multi-core CPUs, the number of concurrently executing processes is rapidly increasing. Unlike processes running in a server environment, those executing in a multi-core desktop or a multi-core mobile platform have various correlations. Therefore, it is crucial to consider correlations among concurrently running processes. In this paper, we exploit the property that for a given created location in the binary image of the parent process, the average running time of child processes residing in the run-queue differs. We claim that this property can be exploited to improve the overall system performance by running processes that have a relatively short running time before those with a longer running time. Experimental results verified that the running time was actually improved by 11%.

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Demand-based schedulability analysis for real-time multi-core scheduling

Lee

Shin

2014

Journal of Systems and Software

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Bounding Worst-Case Performance for Multi-Core Processors with Shared L2 Instruction Caches

Cited by 3 publications

References 34 publications

Counter-Based Approaches for Efficient WCET Analysis of Multicore Processors with Shared Caches

Counter-Based Approaches for Efficient WCET Analysis of Multicore Processors with Shared Caches

A Technique for Fast Process Creation Based on Creation Location

Demand-based schedulability analysis for real-time multi-core scheduling

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