Bounds for the 1-norm of the inverses of some triangular matrices

Reed-Solomon erasure codes (RS-EC) are widely used in packet communication and storage systems to recover erasures. When the RS-EC decoder is implemented on a FieldProgrammable Gate Array (FPGA) in a space platform, it will suffer Single Event Upsets (SEUs) that can cause failures. In this paper, the reliability of an RS-EC decoder implemented on an FPGA when there are errors in the user memory is firstly studied. Then a fault detection and localization scheme is proposed based on partial re-encoding for the faults in user memory of the RS decoder. Furthermore, check bits are added in the generator matrix to improve the fault location performance. Theoretical analysis shows that the scheme could detect most faults with small missing and false detection probability. Experimental results on a case study show that more than 90% faults on user memory could be tolerated by the decoder, and the all other faults can be detected by the fault detection scheme when the number of erasures is less than the correction capability of the code. Although false alarms exist (with probability smaller than 4%), they can be used to avoid faults accumulation. Finally, the fault location scheme could accurately locate all the faults. The theoretical estimates are very close to the experiment results, which verifies the correctness of the analysis done.

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Design of FPGA-Implemented Reed–Solomon Erasure Code (RS-EC) Decoders With Fault Detection and Location on User Memory

Gao

Zhang

Cheng

et al. 2021

IEEE Trans. VLSI Syst.

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Bounds for the 1-norm of the inverses of some triangular matrices

Cited by 1 publication

References 7 publications

Design of FPGA-Implemented Reed–Solomon Erasure Code (RS-EC) Decoders With Fault Detection and Location on User Memory

Design of FPGA-Implemented Reed–Solomon Erasure Code (RS-EC) Decoders With Fault Detection and Location on User Memory

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