2018 IEEE International Solid - State Circuits Conference - (ISSCC) 2018
DOI: 10.1109/isscc.2018.8310399
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Brain-inspired computing exploiting carbon nanotube FETs and resistive RAM: Hyperdimensional computing case study

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Cited by 103 publications
(44 citation statements)
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“…It has been shown that HD computing degrades very gracefully in the presence of temporary and permanent faults compared to a baseline KNN classifier for the language recognition task: by injecting the intermittent hardware-induced errors in both classifiers, HD computing tolerates 8.8× higher probability of failure per individual memory cells [24]; considering the permanent hard errors, HD computing tolerates 60× higher probability of failures [7]. The robust operation under low SNR conditions and high variability perfectly matches with emerging nanotechnologies promising to deliver substantial energy savings [7], [5], [6].…”
Section: E Energy Efficiencymentioning
confidence: 68%
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“…It has been shown that HD computing degrades very gracefully in the presence of temporary and permanent faults compared to a baseline KNN classifier for the language recognition task: by injecting the intermittent hardware-induced errors in both classifiers, HD computing tolerates 8.8× higher probability of failure per individual memory cells [24]; considering the permanent hard errors, HD computing tolerates 60× higher probability of failures [7]. The robust operation under low SNR conditions and high variability perfectly matches with emerging nanotechnologies promising to deliver substantial energy savings [7], [5], [6].…”
Section: E Energy Efficiencymentioning
confidence: 68%
“…An architecture based on HD computing can be seen as an extremely wide dataflow processor with small instruction set of bit-level operations. Further, logic can be tightly integrated with the memory and all computations are fully distributed that can save energy [6], [7]. This forms a fundamental departure from the traditional von Neumann architectures where data has to be transported to the processing unit and back, creating the infamous memory wall.…”
Section: E Energy Efficiencymentioning
confidence: 99%
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“…These make it well-suited for efficient biosignal processing [17], e.g., 2× lower energy at iso-accuracy when compared to a highly-optimized SVM on an ARM Cortex M4 [15]. Larger energy saving is achieved by using emerging 3D nanoscale devices [18], [19]. HD computing has been applied to various learning and multiclass inference tasks, such as the language identification [22], [23], EMG gesture recognition [14], [15], EEG-based brain-machine interfaces [16], and in general ExG processing [17].…”
Section: B Background Of Hd Computingmentioning
confidence: 99%
“…Despite these benefits, the reported system level demonstrations using CNFET technology have been primarily limited to PMOS-only digital logic implementations such as 3D Nano System (which demonstrated sensing, computing, and memory integrated all on the same chip) [7], and a hyperdimensional computing case study exploiting CNFETs and RRAM [10]. In addition, all reported CNFET CMOS demonstrations have been limited to only individual devices, small-scale circuits, or digital logic.…”
Section: Background and Motivationmentioning
confidence: 99%