“…Also, it is worth noting that the above assumptions are probably only applicable in the non‐field‐plate (NFP) GaN devices, as shown in Figure 1A. To enhance the breakdown voltage and suppress the current collapse, a field‐plate (FP) structure is used, 14,15 and a typical example is shown in Figure 1B. Moreover, to further improve the breakdown voltage and reduce the on‐resistance, the gate‐drain spacing L GD is increased, and the gate‐source spacing L GS is reduced, which results in an asymmetric structure of GaN device 16,17 .…”