Bridged-Grain Polycrystalline Silicon Thin-Film Transistors

Zhao, Shuyun; Meng, Zhiguo; Zhou, Wei; Ho, J.; Wong, Man; Kwok, Hoi‐Sing

doi:10.1109/ted.2013.2258925

Cited by 21 publications

(17 citation statements)

References 18 publications

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“…These great improvements achieved by utilizing the BG structure are mainly attributed to grain size effect, SCE and multijunction effect [6]- [9]. For grain size effect, the doped BG region inside the channel could reduce grain boundary (GB) traps [7], [29] and lower the GB barrier along the current path. Extracted from the inset of Fig.…”

Section: Methodsmentioning

confidence: 99%

Characterization of DC-Stress-Induced Degradation in Bridged-Grain Polycrystalline Silicon Thin-Film Transistors

Zhang

Zhou

Chen

et al. 2014

IEEE Trans. Electron Devices

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In this paper, dc-stress-induced degradation in bridged-grain (BG) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) is systemically characterized and investigated. Compared with normal poly-Si TFTs, BG poly-Si TFTs exhibit better hot-carrier (HC) reliability, better self-heating (SH) reliability, and better negative bias temperature (NBT) instability. Resulting from the heavily doped BG lines inside the active channel, lateral electric field reduction at the drain side, Joule heat diffusion enhancement at the channel length direction, and boron-hydrogen bond formation at interface/grain boundaries are, respectively, responsible for the improved HC reliability, SH reliability, and NBT reliability in BG poly-Si TFTs. In addition, stress V g -dependent HC degradation with fixed stress V d , stress power density-dependent SH degradation, and vertical electrical field-dependent NBT degradation are also examined in both normal poly-Si TFTs and BG poly-Si TFTs. All test results indicate that such high-performance and highly reliable BG poly-Si TFT has a great potential for system-on-panel application.Index Terms-Bridged grain (BG), hot carrier (HC), negative bias temperature instability (NBTI), polycrystalline silicon (poly-Si), self-heating (SH), thin-film transistors (TFTs).

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Section: Methodsmentioning

confidence: 99%

Characterization of DC-Stress-Induced Degradation in Bridged-Grain Polycrystalline Silicon Thin-Film Transistors

Zhang

Zhou

Chen

et al. 2014

IEEE Trans. Electron Devices

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“…

cost. These previous results [11][12][13][14][15][16] reveal that the BG TFTs are promising for advanced AM and SoP applications. In a BG TFT, the channel is divided into several segments and bridged by submicron-scale heavily doped regions, which are called BG lines.

…”

mentioning

confidence: 55%

“…Recently, bridged-grain (BG) technique [11][12][13][14][15][16] has been proposed to improve device performance and reliability in poly-Si TFTs without increasing the thermal budget of crystallization. Recently, bridged-grain (BG) technique [11][12][13][14][15][16] has been proposed to improve device performance and reliability in poly-Si TFTs without increasing the thermal budget of crystallization.…”

mentioning

confidence: 99%

“…However, those methods either involve complicated processes or increase the fabrication cost. Recently, bridged‐grain (BG) technique has been proposed to improve device performance and reliability in poly‐Si TFTs without increasing the thermal budget of crystallization. In a BG TFT, the channel is divided into several segments and bridged by submicron‐scale heavily doped regions, which are called BG lines.…”

mentioning

confidence: 99%

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High‐Performance Polycrystalline Silicon Thin‐Film Transistors without Source/Drain Doping by Utilizing Anisotropic Conductivity of Bridged‐Grain Lines

Zhang

Lin

Deng

et al. 2019

Adv Elect Materials

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cost. Recently, bridged-grain (BG) technique [11][12][13][14][15][16] has been proposed to improve device performance and reliability in poly-Si TFTs without increasing the thermal budget of crystallization. In a BG TFT, the channel is divided into several segments and bridged by submicron-scale heavily doped regions, which are called BG lines. Field effect mobility, on-state current (I on ), and threshold voltage (V th ) can be greatly enhanced, enlarged, and reduced due to the short channel effect and the reduced number of grain boundaries inside the channel. Meanwhile, the leakage current and kink effect are suppressed and decreased due to the drain electric field lowering. These previous results [11][12][13][14][15][16] reveal that the BG TFTs are promising for advanced AM and SoP applications. However, compared with the normal top-gate TFT process, the fabrication of BG TFTs involves one extra ion implantation process to form the doped periodical BG regions using a grating structure as a mask. The source/drain (S/D) doping is realized separately through another self-aligned ion implantation process using the gate layer as the mask. The dual implantation processes increase the complexity and cost of the device fabrication. Moreover, in both normal top-gate TFT process and BG TFT process, the dopant activation condition is limited by the metal gate electrodes. Taking Al for By utilizing anisotropic conductivity of bridged-grain (BG) lines, a polycrystalline silicon (poly-Si) thin-film transistor (TFT) without source/drain (S/D) doping is designed, simulated, and fabricated. In the new design, the current is made to flow along the BG lines in the S/D region and flow perpendicularly to the BG lines in the channel. By taking advantage of the anisotropic conductivity of the BG lines, the S/D doping process is eliminated and the fabrication process cost is reduced. Meanwhile, the advantages of adopting BG lines are maintained. The as-fabricated TFTs without S/D doping exhibit excellent device characteristics, compared with normal TFTs. The reliability of TFTs without S/D doping is also evaluated under hot carrier stress and negative/positive bias stress. Additionally, the proposed new TFT structure allows a wider range of dopant activation conditions.

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“…Consequently, electrical characteristics and reliability issues are two important factors to realize high performance LTPS-TFTs. In order to achieve excellent electrical characteristics, a new bridged-grain (BG) structure is proposed and the higher performances of LTPS-TFTs are observed [3]- [5]. However, the gate induced drain leakage current (GIDL) behavior is always an important issue [6], which not solved with BG structure [5].…”

Section: Introductionmentioning

confidence: 99%

P‐6.6: Effects of lightly Doped Drain Structure in n‐channel ELA Bridged‐Grain Poly‐Si TFTs

Guo

Yan

et al. 2019

Symp Digest of Tech Papers

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We lead the lightly doped drain (LDD) structure into the bridged‐grain (BG) poly‐Si thin film transistor (TFT). This combined structure can restrain the gate induced drain leakage current (GIDL) and the electrical characteristics shows not much sacrifice. A high Ion/Ioff current ratio 3.79×108 is achieved. Besides, the device reliability is improved significantly. Because the lateral electrical field decreases by LDD, lower trap state density is generated in the SiO2/poly‐Si interface and the grain boundaries of poly‐Si near the surface conduction channel, resulting in the stable on‐state drive current (Ion) and drain saturation voltage (Vdsat). All test results indicate that the BG poly‐Si TFT with a LDD structure will work well and has a great potential for system‐on‐panel application.

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Bridged-Grain Polycrystalline Silicon Thin-Film Transistors

Cited by 21 publications

References 18 publications

Characterization of DC-Stress-Induced Degradation in Bridged-Grain Polycrystalline Silicon Thin-Film Transistors

Characterization of DC-Stress-Induced Degradation in Bridged-Grain Polycrystalline Silicon Thin-Film Transistors

High‐Performance Polycrystalline Silicon Thin‐Film Transistors without Source/Drain Doping by Utilizing Anisotropic Conductivity of Bridged‐Grain Lines

P‐6.6: Effects of lightly Doped Drain Structure in n‐channel ELA Bridged‐Grain Poly‐Si TFTs

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