Brief Industry Paper: AXI-Interconnect<sup>RT</sup>: Towards a Real-Time AXI-Interconnect for System-on-Chips

Jiang, Zhe; Audsley, Neil; Shill, Dayu; Yang, Kecheng; Fisher, Nathan; Zheng, Dong

doi:10.1109/rtas52030.2021.00046

Cited by 6 publications

(4 citation statements)

References 7 publications

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“…To address the performance and real-time performance of the Xilinx's AXI-Interconnect IP, literature [18] introduced a real-time AXI-Interconnect for heterogeneous SoCs. This redefines the microstructure of the interconnect by allowing random access buffer transactions and organizing transactions using dedicated hardware units.…”

Section: Interconnectmentioning

confidence: 99%

High performance and low area interconnect structure based on AXI

Zhang,

Cai,

Huang

2024

Workshop on Electronics Communication Engineering (WECE 2023)

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Section: Interconnectmentioning

confidence: 99%

High performance and low area interconnect structure based on AXI

Zhang,

Cai,

Huang

2024

Workshop on Electronics Communication Engineering (WECE 2023)

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“…In this paper, all the FIFOs are with the AXI-lite interface [6] [7]. The signals of AXI-lite interface are shown in Figure 1(a).…”

Section: The Interface Of Synchronous and Asynchronous Fifomentioning

confidence: 99%

“…For AXI bus [7] [16], there could be multiple masters issuing reading commands or writing commands, and the commands from different masters are interleaved. Each command requests multiple reading or writing data packets.…”

Section: Usage Of Synchronous Fifos For Interleaved Axi Reading and W...mentioning

confidence: 99%

Review on the Usage of Synchronous and Asynchronous FIFOs in Digital Systems Design

Hu,

Lei,

Wang

2024

ENG

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First-Input-First-Output (FIFO) buffers are extensively used in contemporary digital processors and System-on-Chips (SoC). There are synchronous FIFOs and asycnrhonous FIFOs. And different sized FIFOs should be implemented in different ways. FIFOs are used not only for the pipeline design within a processor, for the inter-processor communication networks, for example Network-on-Chips (NoCs), but also for the peripherals and the clock domain crossing at the whole SoC level. In this paper, we review the interface, the circuit implementation, and the various usages of FIFOs in various levels of the digital design. We can find that the usage of FIFOs could greatly facilitate the signal storage, signal decoupling, signal transfer, power domain separation and power domain crossing in digital systems. We hope that more attentions are paid to the usages of synchronous and asynchronous FIFOs and more sophististicated usages are discovered by the digital design communities.

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“…The abundance of communication standards introduces lexibility, but at the same time, requires the implementation of an appropriate physical layer for the selected standard. In order to improve communication, SoC FPGA supports industry-standard AXI (Advanced eXtensible Interface) bus [9]. Compared to previously mentioned solutions, i.e.…”

Section: Communication Standards and Hardware Detailsmentioning

confidence: 99%

SoC-FPGA Based Concept of Hardware Aided Quantum Simulation

Długopolski,

Czerski,

Knapik

2024

JAMRIS

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Contemporary industry and science expectations towards technological solutions set the bar high. Current approaches to increasing the computing power of standard systems are reaching the limits of physics known to humankind. Fast, programmable systems with relatively low power consumption are a different concept for performing complex calculations. Highly parallel processing opens up a number of possibilities in the context of accelerating calculations. Application of SoC (System On Chip) with FPGA (Field-Programmable Gate Array) enables to delegate of a part of computations to the gates matrix, thereby expediting processing by using parallelization of hardware operations. This paper presents the general concept of using SoC FPGA systems to support CPU (Central Processing Unit) in many modern tasks. While some tasks might be really hard to implement on an FPGA in a reasonable time, the SoC FPGA platform allows for easy low-level interconnections, and with such virtualized access to the hardware computing resources, it is seen as making FPGAs, or hardware in general, more accessible to engineers accustomed to high-level solutions. The concept presented in the article takes into account the limited resources of cheaper educational platforms, which, however, still provide an interesting and alternative hybrid solution to the problem of parallelization and acceleration of data processing. This allows to overcome encountered limitations and maintain the flexibility known from high-level solutions and high performance achieved with low-level programming, without the need for a high financial background.

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Brief Industry Paper: AXI-Interconnect^RT: Towards a Real-Time AXI-Interconnect for System-on-Chips

Cited by 6 publications

References 7 publications

High performance and low area interconnect structure based on AXI

High performance and low area interconnect structure based on AXI

Review on the Usage of Synchronous and Asynchronous FIFOs in Digital Systems Design

SoC-FPGA Based Concept of Hardware Aided Quantum Simulation

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Brief Industry Paper: AXI-InterconnectRT: Towards a Real-Time AXI-Interconnect for System-on-Chips

Cited by 6 publications

References 7 publications

High performance and low area interconnect structure based on AXI

High performance and low area interconnect structure based on AXI

Review on the Usage of Synchronous and Asynchronous FIFOs in Digital Systems Design

SoC-FPGA Based Concept of Hardware Aided Quantum Simulation

Contact Info

Product

Resources

About

Brief Industry Paper: AXI-Interconnect^RT: Towards a Real-Time AXI-Interconnect for System-on-Chips