Logic testing involves the process of testing the digital logic portion of a circuit under test (CUT). The digital logic can be reconfigured in test mode to include
test logic
to improve the testability and test quality of the circuit. Logic testing typically consists of applying a set of test stimuli to the inputs of the digital logic while analyzing the output responses. Depending on needs, both input test stimuli and output response analysis can be generated and performed inside the chip. Circuits that produce the correct output responses for all input stimuli pass the test and are considered to be fault free. Those circuits that fail to produce a correct response at any point during the test sequence are assumed to be faulty.