BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate Control

Khandelwal, Sourabh; Chauhan, Yogesh Singh; Lu, Darsen D.; Venugopalan, Sriramkumar; Karim, Muhammed Ahosan Ul; Sachid, Angada B.; Nguyen, Bich‐Yen; Rozeau, O.; Faynot, O.; Niknejad, Ali M.; Hu, Chenming

doi:10.1109/ted.2012.2198065

Cited by 94 publications

(22 citation statements)

References 24 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…With notations defined in Table 1, we obtain three coupled equations (1)-(3) from the integrations of Poisson's equation and boundary conditions, as in [10], but with a different form for equation (3). Gate electrostatic potential normalized to φ T x g2…”

Section: Calculation Of Surface Potentialsmentioning

confidence: 99%

“…To take full advantage of this latter benefit, circuit designers need compact models that describe properly the transistor behavior for a wide range of back bias. In previously reported works on complete compact models, the interface between the body and the buried oxide is assumed always depleted [3,4], which provides correct results in reverse and low forward back bias (FBB) range. However, when a strong FBB is applied, inversion occurs first at the back interface [5], which has a significant impact on device characteristics (Fig.1).…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

UTSOI2: A complete physical compact model for UTBB and independent double gate MOSFETs

Poiroux

Rozeau

Martinie

et al. 2013

2013 IEEE International Electron Devices Meeting

View full text Add to dashboard Cite

In this paper, we present the first complete compact model dedicated to Ultra-Thin Body and Box and Independent Double Gate MOSFETs based on an explicit formulation of front and back surface potentials that is valid and extremely accurate in all operation regimes. The model provides physics-based consistent description of DC and AC device characteristics; it has been extensively validated against TCAD and hardware data, and fulfills standard requirements from quality assurance and convergence tests for circuit design.

show abstract

Section: Calculation Of Surface Potentialsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

UTSOI2: A complete physical compact model for UTBB and independent double gate MOSFETs

Poiroux

Rozeau

Martinie

et al. 2013

2013 IEEE International Electron Devices Meeting

View full text Add to dashboard Cite

show abstract

“…The improvement in RF characteristics has been verified down to liquid-nitrogen temperature (77 K) [21]. In addition to device characterization, it is mandatory that industry-standard compact models [22,23,24] become compatible with cryogenic temperatures, to achieve optimal cryogenic CMOS designs controlling a large number of qubits. To date, important temperature-related phenomena have been included only by fitting the characteristics using the existing temperature-scaling laws available in industry-standard compact MOS transistor models dedicated to room-temperature operation, i.e., for bulk [25] and double-gate MOSFET [26].…”

mentioning

confidence: 99%

Characterization and modeling of 28-nm FDSOI CMOS technology down to cryogenic temperatures

Beckers

Jazaeri

Bohuslavskyi

et al. 2019

Solid-State Electronics

View full text Add to dashboard Cite

This paper presents an extensive characterization and modeling of a commercial 28-nm FDSOI CMOS process operating down to cryogenic temperatures. The important cryogenic phenomena influencing this technology are discussed. The low-temperature transfer characteristics including body-biasing are modeled over a wide temperature range (room temperature down to 4.2 K) using the design-oriented simplified-EKV model. The trends of the free-carrier mobilities versus temperature in long and short-narrow devices are extracted from dc measurements down to 1.4 K and 4.2 K respectively, using a recently-proposed method based on the output conductance. A cryogenic-temperature-induced mobility degradation is observed on long pMOS, leading to a maximum hole mobility around 77 K. This work sets the stage for preparing industrial design kits with physicsbased cryogenic compact models, a prerequisite for the successful co-integration of FDSOI CMOS circuits with silicon qubits operating at deep-cryogenic temperatures.The birth of CMOS-compatible qubits in silicon [1,2,3,4] has rebooted the interest in cryogenic CMOS electronics for computing applications. Since the 1970s, MOSFET devices have been under investigation at cryogenic temperatures for use in custom applications, such as low-noise scientific equipment, spacecraft, power conversion etc. [5,6,7,8,9]. However, despite its many benefits for reaching high-performance and low-power computing [10], cryogenic cooling did not stay into practice for computing, abandoning the trend set by the ETA-10 liquid-nitrogen-cooled supercomputer [11].Nowadays, co-integrating qubits and CMOS circuits on the same substrate can greatly aid the development of scalable quantum computers featuring massive parallelism and error correction [12,13,14]. In this context, a silicon-on-insulator (SOI) platform is particularly attractive since the back gate provides additional control over the electron-spin qubit, trapped under the front gate of a SOI (nanowire) MOSFET[12,15,16]. To integrate the control circuits with quantum devices working at deep-cryogenic temperatures, regular SOI MOSFETs need to demonstrate reliable digital, analog and RF functionalities at such low temperatures. Using SOI cryogenic control electronics, the back gate can prove a useful tool to control the threshold voltage and hence the power consumption in circuits integrated close to the qubits [17], benefiting qubit coherence time by lowering generated noise. The main focus is on advanced ultra-thin body fully-depleted SOI (FDSOI) technology, e.g., the 28-nm node, to enable ultimate scalability of the resulting hybrid quantum-classical system [16,18].The 28-nm node, presently considered the ideal node for analog and RF applications at room temperature [19], has recently been tested for digital and analog functionality down to liquid-helium temperature (4.2 K) [17], and millikelvin temperature (20 mK) [20]. The improvement in RF characteristics has been verified down to liquid-nitrogen temperature (77 K) [21]. In addition to device c...

show abstract

“…IV). These results pave the way towards the extension of industry-standard compact models down to the deep-cryogenic temperature regime [9], [10]. This will allow to explore optimal cryo-CMOS circuit designs for multiple applications, in particular qubit-control systems.…”

Section: Introductionmentioning

confidence: 82%

Design-oriented modeling of 28 nm FDSOI CMOS technology down to 4.2 K for quantum computing

Beckers

Jazaeri

Bohuslavskyi

et al. 2018

2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)

View full text Add to dashboard Cite

In this paper a commercial 28-nm FDSOI CMOS technology is characterized and modeled from room temperature down to 4.2 K. Here we explain the influence of incomplete ionization and interface traps on this technology starting from the fundamental device physics. We then illustrate how these phenomena can be accounted for in circuit device-models. We find that the design-oriented simplified EKV model can accurately predict the impact of the temperature reduction on the transfer characteristics, back-gate sensitivity, and transconductance efficiency. The presented results aim at extending industry-standard compact models to cryogenic temperatures for the design of cryo-CMOS circuits implemented in a 28 nm FDSOI technology.

show abstract

BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate Control

Cited by 94 publications

References 24 publications

UTSOI2: A complete physical compact model for UTBB and independent double gate MOSFETs

UTSOI2: A complete physical compact model for UTBB and independent double gate MOSFETs

Characterization and modeling of 28-nm FDSOI CMOS technology down to cryogenic temperatures

Design-oriented modeling of 28 nm FDSOI CMOS technology down to 4.2 K for quantum computing

Contact Info

Product

Resources

About