Bubble Budgeting: Throughput Optimization for Dynamic Workloads by Exploiting Dark Cores in Many Core Systems

Abstract

Abstract-All the cores of a many-core chip cannot be active at the same time, due to reasons like low CPU utilization in server systems and limited power budget in dark silicon era. These free cores (referred to as bubbles) can be placed near active cores for heat dissipation so that the active cores can run at a higher frequency level, boosting the performance of applications that run on active cores. Budgeting inactive cores (bubbles) to applications to boost performance has the following three challenges. First, the number of bubbles varies due to open workloads. Second, communication distance increases when a bubble is inserted between two communicating tasks (a task is a thread or process of a parallel application), leading to performance degradation. Third, budgeting too many bubbles as coolers to running applications leads to insufficient cores for future applications. In order to address these challenges, in this paper, a bubble budgeting scheme is proposed to budget free cores to each application so as to optimize the throughput of the whole system. Throughput of the system depends on the execution time of each application and the waiting time incurred for newly arrived applications. Essentially, the proposed algorithm determines the number and locations of bubbles to optimize the performance and waiting time of each application, followed by tasks of each application being mapped to a core region. A Rollout algorithm is used to budget power to the cores as the last step. Experiments show that our approach achieves 50% higher throughput when compared to state-of-the-art thermal-aware runtime task mapping approaches. The runtime overhead of the proposed algorithm is in the order of 1M cycles, making it an efficient runtime task management method for large-scale many-core systems.

A Survey of System Level Power Management Schemes in the Dark-Silicon Era for Many-Core Architectures

“…TSP worst case mapping is computed based on the number of active cores, their position, and the influence of neighbouring cores temperature. Therefore, TSP is considered as the most optimized thermal constraint because the amount of power the chip can operate on, is based on core alignment which is determined by application mapping [17,18]. Similarly, Wang et al [15] also introduced a new power budgeting technique for DSCSs.…”

“…As previously stated, application mapping ensures that specific nodes are selected on the chip for mapping. This can be done in several ways [17,23,[27][28][29]. Different mapping algorithms produces different results (temperature effects and power budget).…”

“…After conducting the thread-to-core mapping, the ant with the best minimizing Chip Multi Processors (CMP) peak temperature is chosen. The temperature of the results generated by the 5 EAI Endorsed Transactions on Industrial Networks and Intelligent Systems 06 2018 -09 2018 | Volume 5 | Issue 15| e5 Similarly, Wang et al [27] also proposed a threadto-core mapping management system. However, this mapping systems uses two different types of virtual mapping algorithms to estimate the performance of applications when different number of dark cores are used.…”

Dynamic Allocation/Reallocation of Dark Cores in Many-Core Systems for Improved System Performance

“…Moreover, since the power density in many-core chips has skyrocketed, some cores have to be power-gated to ensure, at any given time, the total power consumption does not exceed the allowed chip power budget [3]. Although those inactive or poweredoff cores, referred as dark cores [4], impose challenges for performance tuning, they actually offer some opportunities.…”

“…In anticipation that "cold" dark cores can be used for heat dissipation purposes, when an application is mapped to run on active cores, a few dark cores can also be allocated to the same application. There have been a number of studies on mapping applications to both active and dark cores [4]- [9]. They basically allocate dark cores to applications in the way that the active cores are allowed to operate at higher frequency levels, and thus, achieve higher performance at a cost of higher power consumption.…”