Budget Management with Applications

Chen, Chunhong; Bozorgzadeh, Eli; Srivastava, Ankur; Sarrafzadeh, Majid

doi:10.1007/s00453-002-0964-7

Cited by 18 publications

(20 citation statements)

References 11 publications

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“…Maximal budgeting solution Ñ can be obtained by applying different algorithms such as MISA algorithm [3] and ZSA algorithm [4]. Lemma 3: In a maximal budgeting´ Ñ µ, each node (except PIs and POs) has at least one critical incoming edge and at least one critical outgoing edge.…”

Section: Delay Budget Re-assignmentmentioning

confidence: 99%

“…All the proposed algorithms are heuristic sub-optimal algorithms. There are heuristic algorithms in literature and industry to solve the delay budgeting problem such as MISA [3] and ZSA [4] algorithms. In maximum delay budgeting, the objective is to maximize the value of an expression, which is a function of budgets associated with the nodes/edges in a graph.…”

Section: Introductionmentioning

confidence: 99%

“…The solution is not optimal and can be far away from optimal result. MISA algorithm proposed in [3] finds the total budget in the graph with a more sophisticated and intuitive technique using maximum independent set in the graph. MISA algorithm finds a potential slack, which correlates strongly with the total budget in the graph.…”

Section: Introductionmentioning

confidence: 99%

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Optimal Integer Delay-Budget Assignment on Directed Acyclic Graphs

Bozorgzadeh

Ghiasi

Takahashi

et al. 2004

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Excess delay that each component of a design can tolerate under a given timing constraint is referred to as delay budget. Delay budgeting has been widely exploited to improve the design quality in VLSI CAD flow. The objective of the delay budgeting problem investigated in this paper is to maximize the total delay budget assigned to each node in a directed acyclic graph under a given timing constraint. Due to discreteness of the timing of the components in the libraries during design optimization flow, discrete solution for delay budgeting is essential. We present an optimal integer delay budgeting algorithm. We prove that the problem can be solved optimally in polynomial time. In addition, we look at different extensions of the delay budgeting problem, such as maximization of weighted summation of delay budgets assigned to the nodes with constraints on lower bound and upper bound on the delay budget allocated to each node. We prove that for both aforementioned extensions, our algorithm can produce an optimal integer solution in polynomial time. Our algorithm is generic and can be applied in different design tasks at different levels of abstraction. We applied our proposed optimal delay budgeting algorithm in library mapping during datapath synthesis on an FPGA platform ,using pre-optimized cores of FPGA libraries. For each application, we go through synthesis and place and route stages in order to obtain accurate results. Our optimal algorithm outperforms ZSA algorithm [4] in terms of area by ½¼± on average for all applications. In some applications, optimal delay budgeting can speedup runtime of place and route up to ¾ times.Index Terms-delay budgeting, timing constraint, core-based design implementations,integer programming.

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Section: Delay Budget Re-assignmentmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Optimal Integer Delay-Budget Assignment on Directed Acyclic Graphs

Bozorgzadeh

Ghiasi

Takahashi

et al. 2004

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…As the literature shows (cf. [18], [19], [20] [17], [22]), most resource allocation activities consist of numerically truncating a larger resource amount into smaller subsets -more or less in analogy with the abstraction hierarchy of a system's/software's design (see ch. 5.4 and Fig.…”

Section: Budgeted Resource Constraints (Brc) As Requiremental Itemsmentioning

confidence: 99%

A decision model for managing and communicating resource restrictions in embedded systems design

Turban¹,

Wolff

Tsakpinis

et al. 2008

2008 International Workshop on Intelligent Solutions in Embedded Systems

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“…Most of the previous slack budgeting approaches are suboptimal heuristics such as Zero-Slack Algorithm (ZSA) [18]. In [12,[19][20], slack budgeting problem in combinatorial circuit is formulated as maximum-independent-set (MIS) on sensitive transitive closure graph. Recently, [21] presented an LP-based slack budgeting and maximized the potential slack by clock skew optimization.…”

Section: Introductionmentioning

confidence: 99%

Simultaneous slack budgeting and retiming for synchronous circuits optimization

Liu

Hong

et al. 2010

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)

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-With the challenges of growing functionality and scaling chip size, the possible performance improvements should be considered in the earlier IC design stages, which gives more freedom to the later optimization. Potential slack as an effective metric of possible performance improvements is considered in this work which, as far as we known, is the first work that maximizes the potential slack by retiming for synchronous sequential circuit. A simultaneous slack budgeting and incremental retiming algorithm is proposed for maximizing potential slack. The overall slack budget is optimized by relocating the FFs iteratively with the MIS-based slack estimation. Compared with the potential slack of a well-known min-period retiming, our algorithm improves potential slack averagely 19.6% without degrading the circuit performance in reasonable runtime. Furthermore, at the expense of a small amount of timing performance, 0.52% and 2.08%, the potential slack is increased averagely by 19.89% and 28.16% separately, which give a hint of the tradeoff between the timing performance and the slack budget. I IntroductionWith the coming up of SoC (system on a chip) and SiP (system in a package), more and more devices trend to be put in the small silicon area while at the same time the clock frequency is pushed even higher. Thus timing, area, and power dissipation, which are the three major design objectives, become even more challenging in modern circuit design. Typically, the goal of performance optimization is either to minimize the clock period within a given area and/or power budget [1][2][3], or to minimize their area and/or power dissipation under timing constraints [4][5][6][7][8][9][10]. Particularly, timing budget is often performed in order to slow down as many components as possible without violating the system's timing constraints. The slowed-down components can be further optimized to improve system's area, power dissipation, or other design quality metrics.For timing-constrained gate-level synthesis, time slack is an effective metric of circuit's potential performance improvement. The slack budgeting problem on a graph has been studied in theory and practice for many different applications, such as timing-driven placement [16][17] budgeting through LP relaxation. [23] proposed combinatorial methods based on net flow approach to handle the slack budget problem. However, the existing slack budgeting algorithms are either used for combinatorial circuit, or limited to fixed FF locations. At the early design stages, there is flexibility to schedule pipeline or timing distribution to obtain more timing slack.As one of the most powerful sequential optimization techniques, retiming was first proposed by Leiserson and Saxe in 1983 [24], which relocates the flip-flops (FFs) in a circuit while preserving its functionality. The past twenty years saw retiming's effectiveness on improving circuits' timing, area, and power characteristics. Recent publications [1] and [3] proposed a very efficient retiming algorithm for min...

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Budget Management with Applications

Cited by 18 publications

References 11 publications

Optimal Integer Delay-Budget Assignment on Directed Acyclic Graphs

Optimal Integer Delay-Budget Assignment on Directed Acyclic Graphs

A decision model for managing and communicating resource restrictions in embedded systems design

Simultaneous slack budgeting and retiming for synchronous circuits optimization

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