Buffer stage for fast response LDO

An improved fast transient response low dropout voltage regulator

“…Diagram for a fast transient response LDO is shown in the Figure 2 [8]. For any fast transient response LDO topology the critical part is the design of the buffer stage.…”

“…Simplest buffer implementation can be the source follower configuration. Major drawback with this buffer implementation is that it consumes one threshold voltage plus overdrive voltage that is required by the NMOS to operate in saturation and narrows down the output swing which deteriorates the signal to noise ratio (SNR), and also the power supply rejection becomes bad due to body effect (also called back gate effect) [8]. The power supply rejection can be improved considerably by making use of triple well technology where the bulk of the NMOS can be tied separately, but that is an expensive approach and problem of reduced output swing still remains.…”

“…The power supply rejection can be improved considerably by making use of triple well technology where the bulk of the NMOS can be tied separately, but that is an expensive approach and problem of reduced output swing still remains. Another possible solution is to use an unbuffered operational amplifier (OPAMP) in a unity gain configuration [8]. The output resistance of the unity gain buffer is equal to the output resistance of the OPAMP divided by loop gain which can be made very high to get smaller output resistance.…”

“…This small output resistance generates smaller time constant at the gate of the PMOS which allows faster charging and discharging of the large load capacitance (parasitic gate capacitance of the large PMOS driver); hence the LDO can respond faster to the changing load conditions. This buffer stage is capable of providing rail to rail output so the maximum current can be used for charging or discharging of the parasitic capacitance CP that improves slewing [8]. …”

“…Like in implementation of [8] where NMOS used in buffer stage are low-threshold devices, here the design has been done by using generic CMOS technology, so all the devices are of standard threshold. In implementation [8] extra PMOS device is used in the buffer stage between PMOS m23 and NMOS m22 (see Figure 4), but the channel length used here is 0.2um which can introduce drain current variations due to channel length modulation effect. So to avoid this problem we can remove the extra PMOS used in [8].…”