Buffered clock tree for high quality IC design

Chaturvedi, Rishi; Hu, Jiang

doi:10.1109/isqed.2004.1283704

Cited by 40 publications

(44 citation statements)

References 23 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…We integrate some known techniques on clock routing [10][11][12] with our skew tuning technique described in Section 4 to facilitate better solution quality of link insertions. An important ingredient is a balanced tree structure as illustrated in Figure 5.…”

Section: Link Based Buffered Clock Net-work Constructionmentioning

confidence: 99%

Practical techniques to reduce skew and its variations in buffered clock networks

Venkataraman¹,

Jayakumar²,

Hu³

et al.

ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.

View full text Add to dashboard Cite

Clock skew is becoming increasingly difficult to control due to variations. Link based non-tree clock distribution is a cost-effective technique for reducing clock skew variations. However, previous works based on this technique were limited to unbuffered clock networks and neglected spatial correlations in the experimental validation. In this work, we overcome these shortcomings and make the link based non-tree approach feasible for realistic designs. The short circuit risk and multi-driver delay issues in buffered non-tree clock networks are investigated. Our approach is validated with SPICE based Monte Carlo simulations, considering spatial correlations among variations. The experimental results show that our approach can reduce the maximal skew by 47%, improve the skew yield from 15% to 73% on average with a decrease on the total wire and buffer capacitance.

show abstract

Section: Link Based Buffered Clock Net-work Constructionmentioning

confidence: 99%

Practical techniques to reduce skew and its variations in buffered clock networks

Venkataraman¹,

Jayakumar²,

Hu³

et al.

ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.

View full text Add to dashboard Cite

show abstract

“…The deferred-merging and embedding (DME) technique was proposed in [5], it can achieve the zero clock skew with minimal wirelength. In topology generation, some algorithms were proposed for unbuffered and ungated clock tree in [6], and buffered but ungated clock tree in [7]. In ISPD 2009 clock network synthesis contest [8], a voltage variation related objective named Clock Latency Range (CLR) was formulated.…”

Section: Introductionmentioning

confidence: 99%

Clock Network Synthesis with Concurrent Gate Insertion

Chow

Sham

2011

Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation

View full text Add to dashboard Cite

Abstract. In VLSI digital circuits, clock network plays an important role on the total performance of the chip. Clock skew and power dissipation are two major focuses of concerns in the clock network synthesis. During topology generation, the locations of buffer and gate insertion are usually not available. Despite local optimization, the global performance is limited. In this paper, a novel approach of topology generation with concurrent gate insertion is proposed. Meanwhile, a strict clock slew constraint is applied with comprehensive buffer insertion techniques. By clock gating, the switched capacitance of the clock tree is reduced, with acceptable extra cost caused in controller tree. In experimental results it is shown that our approach has good performance on the reduction of both clock skew and power dissipation.

show abstract

“…Then, a graph theory based method is employed to place buffers in their merging blocks so that the overlaps between buffers can be removed. In [13] and [14], new algorithms are proposed to perform buffering and clock routing simultaneously.…”

Section: Introductionmentioning

confidence: 99%

Low power clock buffer planning methodology in F-D placement for large scale circuit design

Wang¹,

Zhang²,

Cai³

et al. 2008

2008 Asia and South Pacific Design Automation Conference

View full text Add to dashboard Cite

Abstract-Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buffers for robustness against variations. That is, clock buffers are often placed far from ideal locations to avoid overlap with logic cells. As a result, both power dissipation and timing are degraded. In order to solve this problem, we propose a low power clock buffer planning methodology which is integrated with cell placement. A BinDivided Grouping algorithm is developed to construct virtual buffer tree, which can explicitly model the clock buffers in placement. The virtual buffer tree is dynamically updated during the placement to reflect the changes of latch locations. To reduce power dissipation, latch clumping is incorporated with the clock buffer planning. The experimental results show that our method can reduce clock power significantly by 21% on average.

show abstract

Buffered clock tree for high quality IC design

Abstract: In ultra-deep submicron VLSI

Cited by 40 publications

References 23 publications

Practical techniques to reduce skew and its variations in buffered clock networks

Practical techniques to reduce skew and its variations in buffered clock networks

Clock Network Synthesis with Concurrent Gate Insertion

Low power clock buffer planning methodology in F-D placement for large scale circuit design

Contact Info

Product

Resources

About