Building an Efficient Hash Table on the GPU

Alcantara, Dan A.; Волков, В. М.; Sengupta, Shubhabrata; Mitzenmacher, Michael; Owens, John D.; Amenta, Nina

doi:10.1016/b978-0-12-385963-1.00004-6

Cited by 54 publications

(90 citation statements)

References 5 publications

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“…3). 2. We evaluate our approach on seven GPUs spanning three Nvidia architectures, across ten application case-studies, showing that we can provoke errors related to weak memory and discovering previously unknown weak memory issues in two applications (Sec.…”

Section: Introductionmentioning

confidence: 99%

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Exposing errors related to weak memory in GPU applications

Sorensen

Donaldson

2016

Proceedings of the 37th ACM SIGPLAN Conference on Programming Language Design and Implementation

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We present the systematic design of a testing environment that uses stressing and fuzzing to reveal errors in GPU applications that arise due to weak memory effects. We evaluate our approach on seven GPUs spanning three Nvidia architectures, across ten CUDA applications that use fine-grained concurrency. Our results show that applications that rarely or never exhibit errors related to weak memory when executed natively can readily exhibit these errors when executed in our testing environment. Our testing environment also provides a means to help identify the root causes of such errors, and automatically suggests how to insert fences that harden an application against weak memory bugs. To understand the cost of GPU fences, we benchmark applications with fences provided by the hardening strategy as well as a more conservative, sound fencing strategy.

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Section: Introductionmentioning

confidence: 99%

“…(Background on CUDA is provided in Sec. 2.) The application incorporates a spinlock, and correctness depends on the source code ordering between the atomic operations on the lock (lines 19,22) and the memory operations in the critical section (line 15) being preserved.…”

Section: Introductionmentioning

confidence: 99%

Exposing errors related to weak memory in GPU applications

Sorensen

Donaldson

2016

Proceedings of the 37th ACM SIGPLAN Conference on Programming Language Design and Implementation

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“…The parallelization of the hashing technique is usually based on the fact that the indices of the keys can be calculated independently. The study [31] proposes GPU parallelizations of several hashing algorithms, such as "Open adressing", "Chaining" or "Cuckoo hashing". However, these works mainly focus on the speed of the hash table building phase and on subsequent dynamic updates.…”

Section: A Hashing and Parallel Hashingmentioning

confidence: 99%

Perfect Hashing Structures for Parallel Similarity Searches

Tran

Giraud

Varré

2015

2015 IEEE International Parallel and Distributed Processing Symposium Workshop

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Abstract-Seed-based heuristics have proved to be efficient for studying similarity between genetic databases with billions of base pairs. This paper focuses on algorithms and data structures for the filtering phase in seed-based heuristics, with an emphasis on efficient parallel GPU/manycores implementation. We propose a 2-stage index structure which is based on neighborhood indexing and perfect hashing techniques. This structure performs a filtering phase over the neighborhood regions around the seeds in constant time and avoid as much as possible random memory accesses and branch divergences. Moreover, it fits particularly well on parallel SIMD processors, because it requires intensive but homogeneous computational operations. Using this data structure, we developed a fast and sensitive OpenCL prototype read mapper.

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“…At the same time, it is expressive enough to implement all required operations: All major database operators -including aggregation [24], selection [19], sorting [16,22,30,31], joins [20], hashing [2,3,14] and string operations [10] -, have been shown to be efficiently implementable within the constraints of the model. We therefore believe that the kernel programming model is a good choice to form the basis of a hardware-oblivious parallel database engine.…”

Section: The Kernel Programming Modelmentioning

confidence: 99%

“…Our parallel hashing algorithm builds on ideas from [2,3,14]. It begins with an optimistic round, letting each thread insert its keys without any form of synchronization.…”

Section: Hashingmentioning

confidence: 99%

Hardware-oblivious parallelism for in-memory column-stores

Heimel

Saecker²,

Pirk

et al. 2013

Proc. VLDB Endow.

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The multi-core architectures of today's computer systems make parallelism a necessity for performance critical applications. Writing such applications in a generic, hardware-oblivious manner is a challenging problem: Current database systems thus rely on laborintensive and error-prone manual tuning to exploit the full potential of modern parallel hardware architectures like multi-core CPUs and graphics cards. We propose an alternative design for a parallel database engine, based on a single set of hardware-oblivious operators, which are compiled down to the actual hardware at runtime. This design reduces the development overhead for parallel database engines, while achieving competitive performance to hand-tuned systems.We provide a proof-of-concept for this design by integrating operators written using the parallel programming framework OpenCL into the open-source database MonetDB. Following this approach, we achieve efficient, yet highly portable parallel code without the need for optimization by hand. We evaluated our implementation against MonetDB using TPC-H derived queries and observed a performance that rivals that of MonetDB's query execution on the CPU and surpasses it on the GPU. In addition, we show that the same set of operators runs nearly unchanged on a GPU, demonstrating the feasibility of our approach.

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Building an Efficient Hash Table on the GPU

Cited by 54 publications

References 5 publications

Exposing errors related to weak memory in GPU applications

Exposing errors related to weak memory in GPU applications

Perfect Hashing Structures for Parallel Similarity Searches

Hardware-oblivious parallelism for in-memory column-stores

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