Building Rectangular Floorplans–A GraphTheoretical Approach

Abstract

Rectangular dualisation is a technique used to generate rectangular topologies for use in top-down fioorplanning of integrated circuits. In order for this technique to be used in a floorplanning system, its input, the connectivity graph representing an integrated circuit has to fulfill a number of conditions. This paper presents an efficient algorithm that transforms an arbitrary connected graph, representing an integrated circuit, into another graph that is guaranteed to fulfill these conditions and to admit rectangular duals. Effectively, the algorithm solves the global routing problem by using three techniques: passthrough, wiring blocks and collapsed wiring blocks. Resulting floorplans may be passed to a chip assembler and detailed router package to complete the layout. This paper also introduces a novel technique to transform a tree of biconnected sub-graphs into a block neighbourhood graph that is a path. An important aspect of the floorplanning process should be noted when the design is approached topdown, a strategy we encourage. In such cases the designer has incomplete knowledge of the exact content of each block in the floorplan and therefore has to proceed in terms of rectangle shapes and area according to his or her experience.It is important to note here the difference between top-down floorplanning and block placement which is used in bottom-up design approaches. The basic difference resides in that the former assumes that information such as positions of block communication ports, exact block dimensions or shapes need not be known, while the latter is considered as a problem of optimally placing arbitrarily shaped blocks with defined port positions and dimensions. This paper is concerned with the automation of top-99