Built-In Self-Repair Techniques for Heterogeneous Memory Cores

Wang, Zhenyu; Tsai, Yi-Ming; Lu, Shyue-Kung

doi:10.1109/prdc.2009.19

Cited by 8 publications

(3 citation statements)

References 15 publications

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“…However, selection of the faulty line with the largest fault count is the time‐consuming process, because it may need to pick more than one line for repair and have area overhead due to additional local bit map. In essential spare pivoting (ESP) [8, 9], the approach of finding of pivot rows and columns was sequential in nature. It is simple in implementation, which results in smaller area overhead than other RA – algorithms.…”

Section: Introductionmentioning

confidence: 99%

Novel modified memory built in self‐repair (MMBISR) for SRAM using hybrid redundancy‐analysis technique

Pundir

2019

IET Circuits, Devices & Systems

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The article presents a new augmented and improved MMBISR for SRAM using hybrid redundancy analysis (HRA). The presented algorithm is the augmented version of essential spare pivoting (ESP) and local repair most (LRM). The algorithm proposes the best solution by providing optimised set of row and column combination which were suitable for the repairing process. In the proposed redundancy analysis (RA) algorithm, the fault dictionary can be updated or fixed concurrently, according to MBIST needs and supplied control signals. The row and column pivots and repair requests are also serviced according to precedency list prepared by the comparing actions. The comparative analysis with LRM and ESP-RA algorithms shows that the proposed algorithm has reduced complexity and tracing time in terms of implementation and in terms of finding row and column pivots. For the implementation, a MBISR hardware structure is designed and tested using suitable VHDL descriptions that were targeted for Virtex-5, xc5vlx30 FPGA. The results were also justified that the proposed algorithm is quite effective as the repair rate is increased up to 4% compared to the ESP. However, some nominal area penalty is observed as compared to ESP.

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Section: Introductionmentioning

confidence: 99%

Novel modified memory built in self‐repair (MMBISR) for SRAM using hybrid redundancy‐analysis technique

Pundir

2019

IET Circuits, Devices & Systems

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“…Therefore, the yield of embedded memories dominates the whole chip's yield. In the past, fault replacement techniques [2][3][4][5][6][7][8][9][10][11] are usually used for repairing faulty memory cells. In other words, redundant rows/columns are used to replace faulty memory cells.…”

Section: Introductionmentioning

confidence: 99%

“…One promising solution to implement the fault replacement technique is the built-in self-repair (BISR) method. To achieve the goals of BISR, three basic modules including memory built-in self-test (BIST), built-in redundancy analysis (BIRA), and address reconfiguration (remapping) (AR), are usually required [2][3][4][5][6][7][8][9][10][11].…”

Section: Introductionmentioning

confidence: 99%

Fault Scrambling Techniques for Yield Enhancement of Embedded Memories

Jheng

Hashizume

et al. 2013

2013 22nd Asian Test Symposium

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Instead of merely using redundant rows/columns to replace faulty cells, error-correcting codes are also considered an effective technique to cure permanent faults for the enhancement of fabrication yield and reliability of memories. However, if the number of faulty bits in a codeword is greater than 1, the protection capability of the widely used SEC-DED (single-error correction and double-error detection) codes will be limited. In order to cure this dilemma, efficient fault scrambling techniques are proposed in this paper. Unlike the fixed constituting memory cells of a codeword in the conventional EDAC schemes, we try to reconstruct the memory cells of codewords such that each codeword consists of at most one faulty cell. The corresponding scrambling circuits are also proposed and a simulator is developed to evaluate the repair rates and hardware overhead. According to experimental results, the repair rates can be improved significantly with negligible hardware overhead.

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Address Remapping Techniques for Enhancing Fabrication Yield of Embedded Memories

Jheng

Lin

et al. 2018

J Electron Test

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Built-In Self-Repair Techniques for Heterogeneous Memory Cores

Cited by 8 publications

References 15 publications

Novel modified memory built in self‐repair (MMBISR) for SRAM using hybrid redundancy‐analysis technique

Novel modified memory built in self‐repair (MMBISR) for SRAM using hybrid redundancy‐analysis technique

Fault Scrambling Techniques for Yield Enhancement of Embedded Memories

Address Remapping Techniques for Enhancing Fabrication Yield of Embedded Memories

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