Built-in self-test: Early developments and future trends

Muchα, J.

doi:10.1007/bf01232917

Cited by 2 publications

(3 citation statements)

References 10 publications

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“…To make the BIST circuit effective with reduced cost/time in design/testing, four parameters must be considered while developing BIST, namely, fault coverage, number of test patterns generated, overhead in chip area, and performance penalty (Mucha, 1996). The circuitry to generate test vectors is the most important issue in the BIST design.…”

Section: Testingmentioning

confidence: 99%

“…Other benefits that BIST offer are economical burn‐in test, reduced need for ATE, and usability as online and off‐line testing. Although BIST offers some demerits like area overhead, performance penalties, additional design time, and efforts (Mucha, 1996) but the case studies on BIST have justified that its benefits always make up for the cost of BIST.…”

Section: Testingmentioning

confidence: 99%

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VLSI interconnects and their testing: prospects and challenges ahead

Sharma¹,

Kaushik

Sharma

2011

Journal of Engineering, Design and Technology

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PurposeThe purpose of this paper is to explore the functioning of very‐large‐scale integration (VLSI) interconnects and modeling of interconnects and evaluate different approaches of testing interconnects.Design/methodology/approachIn the past, on‐chip interconnect wires were not considered in circuit analysis except in high precision analysis. Wiring‐up of on‐chip devices takes place through various conductors produced during fabrication process. The shrinking size of metal‐oxide semiconductor field effect transistor devices is largely responsible for growth of VLSI circuits. With deep sub‐micron (DSM) technology, the interconnect geometry is scaled down for high wiring density. The complex geometry of interconnects and high operational frequency introduce wire parasitics and inter‐wire parasitics. These parasitics causes delay, power dissipation, and crosstalk that may affect the signal integrity in VLSI system. Accurate analysis, sophisticated design, and effective test methods are the requirement to ensure the proper functionality and reliability of VLSI circuits. The testing of interconnect is becoming important and a challenge in the current technology.FindingsThe effects of interconnect on signal integrity, power dissipation, and delay emerges significantly in DSM technology. For proper performance of the circuit, testing of interconnect is important and emerging challenge in the nanotechnology era. Although some work has been done for testing of interconnect, however, it is still an open area to test the parasitics effects of VLSI/ultra‐large‐scale integration interconnects. Efforts are required to analyze and to develop test methods for crosstalk, delay and power dissipation in current technology with solutions to minimize this effect.Originality/valueThis paper reviews the functioning of VLSI interconnects from micrometer to nanometer technology. The development of various interconnect models from simple short circuit to latest resistance inductance capacitance transmission line model are discussed. Furthermore, various methodologies such as built‐in self test and other techniques for testing interconnect for crosstalk and delay are discussed.

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Section: Testingmentioning

confidence: 99%

Section: Testingmentioning

confidence: 99%

VLSI interconnects and their testing: prospects and challenges ahead

Sharma¹,

Kaushik

Sharma

2011

Journal of Engineering, Design and Technology

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“…In the age of modern electronics, the use of multilayered high-speed printed circuit boards (PCBs) has become a common practice in sophisticated equipments. So, testing of PCB is essential to test the interconnections and components mounted on it (Xie et al, 2009;Burgess et al, 1995;Mucha, 1996). In 1960s, testing was done manually.…”

Section: Introductionmentioning

confidence: 99%

Boundary scan based testing algorithm to detect interconnect faults in printed circuit boards

Sharma¹,

Sharma

Kaushik

et al. 2011

Circuit World

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Purpose -This paper aims to address the various issues of board-level (off-chip) interconnects testing. A new algorithm based on the boundary scan architecture is developed to test off-chip interconnect faults. The proposed algorithm can easily diagnose which two interconnects are shorted. Design/methodology/approach -The problems in board-level interconnects testing are not simple. A new algorithm is developed to rectify some of the problems in existing algorithms. The proposed algorithm to test board-level interconnect faults is implemented using Verilog on Modelsim software. The output response of each shorting between different wires of different nodes is different, which is the basis of fault detection by the proposed algorithm. The test vectors are generated by the test pattern generator and these test vectors are different for different nodes. This work implements built in self test using boundary scan technique. Findings -The dominant-1 (wired-OR, denoted as WOR), dominant-0 (wired-AND, denoted as WAND) and stuck-at faults are tested using the proposed algorithm. The proposed algorithm is also compared with the several algorithms in the literature, i.e. modified counting, walking one's algorithm and others. This paper's results are found to be better than the existing algorithms.Research limitations/implications -The limitation of the proposed algorithm is that, at any time, the faults on any seven nodes can be tested to avoid aliasing. So, the groups are formed out of total nodes, in a multiple of seven to carry out the testing of faults. Practical implications -The proposed algorithm is free from the problems of syndromes and utilizes a smaller number of test vectors. Originality/value -Various existing algorithms namely modified counting, walking one's algorithm and others are discussed. A new algorithm is developed which can easily detect board-level dominant-1 (WOR), dominant-0 (WAND) and stuck-at faults. The proposed algorithm is completely free from aliasing and confounding syndromes.

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Built-in self-test: Early developments and future trends

Cited by 2 publications

References 10 publications

VLSI interconnects and their testing: prospects and challenges ahead

VLSI interconnects and their testing: prospects and challenges ahead

Boundary scan based testing algorithm to detect interconnect faults in printed circuit boards

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