Bulk‐Switching Memristor‐Based Compute‐In‐Memory Module for Deep Neural Network Training

Abstract

The need for deep neural network (DNN) models with higher performance and better functionality leads to the proliferation of very large models. Model training, however, requires intensive computation time and energy. Memristor‐based compute‐in‐memory (CIM) modules can perform vector‐matrix multiplication (VMM) in situ and in parallel, and have shown great promises in DNN inference applications. However, CIM‐based model training faces challenges due non‐linear weight updates, device variations, and low‐precision in analog computing circuits. In this work, we experimentally implement a mixed‐precision training scheme to mitigate these effects using a bulk‐switching memristor CIM module. Low‐precision CIM modules are used to accelerate the expensive VMM operations, with high precision weight updates accumulated in digital units. Memristor devices are only changed when the accumulated weight update value exceeds a pre‐defined threshold. The proposed scheme is implemented with a system on chip (SoC) of fully integrated analog CIM modules and digital sub‐systems, showing fast convergence of LeNet training to 97.73%. The efficacy of training larger models is evaluated using realistic hardware parameters and shows that that analog CIM modules can enable efficient mix‐precision DNN training with accuracy comparable to full‐precision software trained models. Additionally, models trained on chip are inherently robust to hardware variations, allowing direct mapping to CIM inference chips without additional re‐training.This article is protected by copyright. All rights reserved

Memristor‐Based Neuromorphic Chips

“…Wu et al established a system comprising 4 tiles of RRAM crossbar arrays, which are used to be CIM tiles, together with another necessary peripheral circuits. [101] As shown in Figure 5a, the AXI bus incorporates four separate CIM tiles as self-contained IP. Furthermore, an on-chip RISC-V core functions as the central controller for programming and computing tasks pertaining to the CIM tiles.…”

“…Furthermore, an on-chip RISC-V core functions as the central controller for programming and computing tasks pertaining to the CIM tiles. This modular design allows for scalability by integrating [101] Copyright 2023, Wiley-VCH. b) The architecture of the tiled memristor chip with the STELLAR scheme for efficient improvement learning.…”

“…Panel (a) reproduced with permission. [ 101 ] Copyright 2023, Wiley‐VCH. b) The architecture of the tiled memristor chip with the STELLAR scheme for efficient improvement learning.…”

“…An on-chip RISC-V core controls the programming and computing of the CIM modules. Panel (a) reproduced with permission [101]. Copyright 2023, Wiley-VCH.…”

PowerGAN: A Machine Learning Approach for Power Side‐Channel Attack on Compute‐in‐Memory Accelerators

“…To balance accuracy and inference efficiency, the weights and input activations are typically quantized to 8 bits, which has been shown to cause minor accuracy losses, especially when coupled with quantization‐aware training techniques. [ 24 ] Since a single RRAM cell considered here only offers 4‐bit storage (Figure 2c), two cells are used to store one weight value. Figure 2f illustrates the mapping scheme for a convolution layer.…”