Bus-driven floorplanning with thermal consideration

Wu, Pei-Chih; Ho, Tsung-Yi

doi:10.1016/j.vlsi.2012.11.002

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Cited by 3 publications

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“…It shows that clock trees designed using standard methodology with assumption of a uniform on-die temperature may suffer from significant skew violations. Wu et al [24] propose a bus-driven floorplanning method for multi-core SoC designs considering thermal distribution of the chip.…”

Section: Related Workmentioning

confidence: 99%

Temperature variation aware multi-scale delay, power and thermal analysis at RT and gate level

2015

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Section: Related Workmentioning

confidence: 99%

Temperature variation aware multi-scale delay, power and thermal analysis at RT and gate level

2015

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Fast thermal analysis for fixed-outline 3D floorplanning

Chen

2017

Integration

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Thermal-Driven Floorplanning for Fixed Outline Layouts

Banerjee

Roy

2020

J CIRCUIT SYST COMP

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In the nano-scale era, chip temperature has gained a lot of importance due to various reasons. Localized high temperatures in certain regions, commonly known as hotspots, directly affect the performance and reliability of the chip. The proposed work concentrates on temperature-driven floorplanning of chips because incorporating cooling techniques may lead to increase in cost. The proposed approach attempts to evenly distribute power dense components across the chip area in order to suppress hotspots and at the same time generate a layout with aspect ratio nearly 1, as is required in the present day floorplanning scenario. The positions of the blocks in the layout are generated using Boolean Satisfiability (SAT). Apart from peak temperature, wirelength being an important cost factor is also taken into consideration. The proposed technique is successful in decreasing the wirelength and peak temperature for large GSRC, MCNC and IBM HB[Formula: see text] benchmarks.

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Bus-driven floorplanning with thermal consideration

Cited by 3 publications

References 25 publications

Temperature variation aware multi-scale delay, power and thermal analysis at RT and gate level

Temperature variation aware multi-scale delay, power and thermal analysis at RT and gate level

Fast thermal analysis for fixed-outline 3D floorplanning

Thermal-Driven Floorplanning for Fixed Outline Layouts

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