2015
DOI: 10.1108/jedt-05-2013-0040
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Bus encoder design for crosstalk and power reduction in RLC modelled VLSI interconnects

Abstract: Purpose – This paper aims to reduce the worst-case crosstalk effects for resistance, inductance and capacitance (RLC) interconnects using the bus encoding technique. In current nanoscale technology, power dissipation, propagation delay and crosstalk performance of interconnects determine the overall performance of a chip. Signal integrity issues due to crosstalk in the form of voltage glitches, overshoots, undershoots, undesirable noise, propagation speed ups and downs, etc. are some of the maj… Show more

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