Bus encoding architecture for low-power implementation of an AMBA-based SoC platform

Osborne, S.; Erdogan, A.T.; Arslan, Tughrul; Robinson, D.

doi:10.1049/ip-cdt:20020448

Cited by 17 publications

(5 citation statements)

References 15 publications

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“…The affirmation of the PSEL flag shows the start of the group stage. The transport goes hooked on the SETUP stage whilst the information exchange is necessary [11][12]. The P WRITE, PADDR along with PW DATA are additionally given amid this stage.…”

Section: Existed Methodsmentioning

confidence: 99%

Ultra Low Power and High Efficiency Advanced Microcontroller Design using Amba Architecture

Babu¹,

Rao²,

Rao³

2019

IJRTE

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The ARM Advanced Microcontroller Bus Architecture (AMBA) is an open-criterion, on-chip interrelate particle particular in favor of the association also the board of useful squares in framework on a chip (SoC) plans. It encourages improvement of multi processor plans through expansive quantities of manager as well as peripherals among a transport design. Seeing as its commencement, the extent of AMBA has, regardless of its name, disappeared a long way past microcontroller gadgets. Nowadays, AMBA is broadly utilized on a scope of ASIC along with SoC divisions incorporating requests processors utilized in current convenient cell phones like advanced mobile phones. The structure comprises of at least one CPUs, GPUs or flag processors, autonomous, to permit reuse of IP centers, fringe and framework full scale cells crosswise over differing IC forms, supporting superior and low power on-chip correspondence.

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Section: Existed Methodsmentioning

confidence: 99%

Ultra Low Power and High Efficiency Advanced Microcontroller Design using Amba Architecture

Babu¹,

Rao²,

Rao³

2019

IJRTE

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“…There is a large body of work that addresses power consumption of global bus lines [4,5,6,7,8,9,10], or the interaction of global bus lines with other components, such as processor caches [11,12]. As mentioned earlier, these techniques do not consider the power consumption of the communication architecture in its entirety.…”

Section: Related Workmentioning

confidence: 98%

Power analysis of system-level on-chip communication architectures

Lahiri

Raghunathan

2004

Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis - CODES+ISSS

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For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumption. Managing and optimizing this important component of SoC power requires a detailed understanding of the characteristics of its power consumption.Various power estimation and low-power design techniques have been proposed for the global interconnects that form part of SoC communication architectures (e.g., low-swing buses, bus encoding, etc). While effective, they only address a limited part of communication architecture power consumption. A state-of-the-art communication architecture, viewed in its entirety, is quite complex, comprising several components, such as bus interfaces, arbiters, bridges, decoders, and multiplexers, in addition to the global bus lines. Relatively little research has focused on analyzing and comparing the power consumed by different components of the communication architecture.In this work, we present a systematic evaluation and analysis of the power consumed by a state-of-the-art communication architecture (the AMBA onchip bus), using a commercial design flow. We focus on developing a quantitative understanding of the relative contributions of different communication architecture components to its power consumption, and the factors on which they depend. We decompose the communication architecture power into power consumed by logic components (such as arbiters, decoders, bus bridges), global bus lines (that carry address, data, and control information), and bus interfaces. We also perform studies that analyze the impact of varying application traffic characteristics, and varying SoC complexity, on communication architecture power. Based on our analyses, we evaluate different techniques for reducing the power consumed by the on-chip communication architecture, and compare their effectiveness in achieving power savings at the system level. In addition to quantitatively reinforcing the view that on-chip communication is an important target for system-level power optimization, our work demonstrates (i) the importance of considering the communication architecture in its entirety, and (ii) the opportunities that exist for power reduction through careful communication architecture design.

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“…The AMBA bus specification is an open standard and is freely available from ARM. Currently, AMBA [5] has numerous third-party support, is adopted by many ARM partners, and has become one of the most widely supported existing interconnect standards in SoC designs based on ARM processor cores.…”

Section: 2ahb Bus Featurementioning

confidence: 99%

Design and implementation of Wishbone-AHB bus bridge

Wang

2023

Third International Conference on Digital Signal and Computer Communications (DSCC 2023)

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In SoC design, in order to enable data exchange and communication between IPs integrated into different on-chip bus standards, a corresponding bus bridge is required to enable their interaction. This paper describes the design structure and implementation method of the Wishbone-AHB bus bridge based on the widely used AMBA bus and Wishbone bus, completes the protocol conversion of different bus standards, realizes the matching and timing adjustment between different bus interface signals at both ends, and performs the functional verification under the iverilog tool, and the simulation results show that the bus bridge design meets the requirements. The simulation results show that the design of the bus bridge meets the requirements.

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Bus encoding architecture for low-power implementation of an AMBA-based SoC platform

Cited by 17 publications

References 15 publications

Ultra Low Power and High Efficiency Advanced Microcontroller Design using Amba Architecture

Ultra Low Power and High Efficiency Advanced Microcontroller Design using Amba Architecture

Power analysis of system-level on-chip communication architectures

Design and implementation of Wishbone-AHB bus bridge

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