Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency

Abstract

Data caches in general-purpose microprocessors often contain mostly dead blocks and are thus used inefficiently. To improve cache efficiency, dead blocks should be identified and evicted early. Prior schemes predict the death of a block immediately after it is accessed; however, these schemes yield lower prediction accuracy and coverage. Instead, we find that predicting the death of a block when it just moves out of the MRU position gives the best tradeoff between timeliness and prediction accuracy/coverage. Furthermore, the individual reference history of a block in the L1 cache can be irregular because of data/control dependence. This paper proposes a new class of dead-block predictors that predict dead blocks based on bursts of accesses to a cache block. A cache burst begins when a block becomes MRU and ends when it becomes non-MRU. Cache bursts are more predictable than individual references because they hide the irregularity of individual references. When used at the L1 cache, the best burst-based predictor can identify 96% of the dead blocks with a 96% accuracy. With the improved dead-block predictors, we evaluate three ways to increase cache efficiency by eliminating dead blocks early: replacement optimization, bypassing, and prefetching. The most effective approach, prefetching into dead blocks, increases the average L1 efficiency from 8% to 17% and the L2 efficiency from 17% to 27%. This increased cache efficiency translates into higher overall performance: prefetching into dead blocks outperforms the same prefetch scheme without dead-block prediction by 12% at the L1 and by 13% at the L2.

A DVFS-aware cache bypassing technique for multiple clock domain mobile SoCs

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Sharing and Hit based Prioritizing Replacement Algorithm for Multi-Threaded Applications

“…But it does not attach any importance to shared data. Elimination of the dead-lines (or) the lines which will never be accessed by the processor in the near future [3,4,11] can greatly enhance the performance of cache memory. Livio Soares et al [3] have proposed a technique to get rid of the dead-lines but they work from OS level and might burden the OS over a period of time.…”

Using Cacheline Reuse Characteristics for Prefetcher Throttling

“…This approach requires additional tables to maintain the past prefetch histories. Liu et al [13] exploited the dead block detection to avoid the negative-effect of prefetching. Prefetching is performed only when the new dead block is detected.…”