Cache design trade-offs for power and performance optimization

Abstract

Abstract

On-Line Failure Detection and Confinement in Caches

“…Such overhead is lower for the large L2 cache because its data arrays are larger, and thus, the relative cost of ROM cells is lower. If wordline partitioning [10,23] was used the area cost would raise, but in any reasonable configuration the area overhead would remain well below 5%. Nevertheless, the area cost can be reduced by reducing the size of the signatures at the expense of some aliasing as explained before.…”

Guaranteeing Hits to Improve the Efficiency of a Small Instruction Cache

“…Thus, an L-cache can hold only a pre-specified and limited number of loops. Line buffers are essentially degenerate L0/filter caches that contain only a single line [19]. The cache access latency of a line buffer is typically prolonged such that a line buffer miss will trigger the corresponding fetch from the L1-IC during the same processor clock cycle.…”

DYNORA: a new caching technique

“…Research has also been done in trade-offs between the cache parameters. [3] gives a case study of cache design trade-offs for power and performance optimizations. Since [5], the focus of research has shifted to run-time reconfiguration methods with on-demand-performance as the keyword.…”

“…Current research is being focused on energy efficient cache architectures ( [1], [3], [5], [9]) and new reconfigurable caching techniques ( [2], [4], [8]). Since circuit level techniques are not able to single handedly provide solutions for achieving the above mentioned ends, higher levels of abstraction namely Algorithmic and Architectural levels [7] are being looked at with increasing interest.…”