Cache-friendly implementations of transitive closure

Abstract

Abstract

Hierarchical Dependency Graphs: Abstraction and Methodology for Mapping Systolic Array Designs to Multicore Processors

“…In this paper, to make our approach intuitive, instead of getting into intricate details of the definitions of dependency graphs, we use an example of a dependency graph to describe our ideas.As the properties used in the example are generic to dependency graphs and also through the case studies, it will be clear that our approach can be applied to any dependency graph. We chose the systolic array design for transitive closure( [2], [4]) as the example. So we briefly describe the problem and its systolic array design below.…”

“…Each macro node has a micro dependency graph (one macro node with micro nodes) inside it. While this abstraction some similarity to tiling ( [4]), this idea can be more easily extended to multiple levels of hierarchies, for new generation high performance computing and supercomputing systems with various levels of parallelism and compute power organization.…”

“…The 70s, 80s saw the upsurge of a revolutionary high performance computing technology -systolic array processors ( [3]) necessitated by increasing demands of speed and performance in these areas. A lot of research work has been done to expose the parallelism and pipelining available in several important scientific computing applications to be exploited by systolic array processors ( [1], [2], [4], [5]). For many of these algorithms, the hardware needed to be flexible and robust to be able to adapt to new problems and also variations in known algorithms.…”

Optimizing graph algorithms for improved cache performance

“…However, it is beneficial to find an estimate of the optimal tile size. A block size selection heuristic for finding this estimate is discussed in [34], and outlined here. • Use the 2:1 rule of thumb from [32] to adjust the cache size to that of an equivalent 4-way set associative cache.…”

“…It has been shown by a number of groups that data layouts tuned to the data access pattern of the algorithm can reduce both TLB and cache misses [7][31] [34]. In the case of the recursive algorithm, the access pattern is matched by a Z-Morton data layout.…”