Cache Locking Content Selection Algorithms for ARINC-653 Compliant RTOS

Dugo, Alexy Torres Aurora; Lefoul, Jean-Baptiste; Magalhães, Felipe Göhring de; Assal, Dahman; Nicolescu, Gabriela

doi:10.1145/3358196

Cited by 6 publications

(7 citation statements)

References 15 publications

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“…Dugo et al [112] have proposed algorithms for ARINC-653 Compliant RTOS to implement static cache locking content selection to reduce the non-determinism and the contention on lower-level memories while improving timing performance. Zhang et al [113] investigated the WCETaware Instruction cache (I-cache) locking problem and proposed an ILP-based dynamic I-cache locking approach for reducing the WCET of a task.…”

Section: ) Cache-locking Techniquesmentioning

confidence: 99%

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A Survey of Techniques for Reducing Interference in Real-Time Applications on Multicore Platforms

et al. 2022

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This survey reviews the scientific literature on techniques for reducing interference in real-time multicore systems, focusing on the approaches proposed between 2015 and 2020. It also presents proposals that use interference reduction techniques without considering the predictability issue. The survey highlights interference sources and categorizes proposals from the perspective of the shared resource. It covers techniques for reducing contentions in main memory, cache memory, a memory bus, and the integration of interference effects into schedulability analysis. Every section contains an overview of each proposal and an assessment of its advantages and disadvantages.INDEX TERMS Real-time systems, architecture, multicore, timing analysis, schedulability analysis, WCET, co-runner interference.

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Section: ) Cache-locking Techniquesmentioning

confidence: 99%

“…[127] use these narrowed WCET bounds to allocate tasks and increase the predictability of memory accesses statically. Dugo et al [112] focus on cache content selection algorithms for cache locking. This approach improves the hit rate and predictability of the caches.…”

Section: ) Summarymentioning

confidence: 99%

A Survey of Techniques for Reducing Interference in Real-Time Applications on Multicore Platforms

et al. 2022

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“…In the other case, static locking [34] creates a cache memory map to be allocated to processes based on profiled log data before runtime. However, dynamic locking can reduce the determinism of real-time systems, such as avionics systems, because it modifies cache locking information at run time [35]. Moreover, there is data or instruction cache locking [33,36] as well as user space or kernel space locking [37].…”

Section: Related Workmentioning

confidence: 99%

“…In avionics systems, several studies have explored bounding the worst-case execution time (WCET), by using cache partitioning to reduce the memory sharing interference. In the single core ARINC-653-based partitioning system, a method has been proposed to reduce the intra-partition cache misses by applying cache locking [35]. In this study, greedy selection and genetic selection algorithms were applied to select the cache areas in each partition for static cache locking.…”

Section: Related Workmentioning

confidence: 99%

Execution Model to Reduce the Interference of Shared Memory in ARINC 653 Compliant Multicore RTOS

et al. 2020

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Multicore architecture is applied to contemporary avionics systems to deal with complex tasks. However, multicore architectures can cause interference by contention because the cores share hardware resources. This interference reduces the predictable execution time of safety-critical systems, such as avionics systems. To reduce this interference, methods of separating hardware resources or limiting capacity by core have been proposed. Existing studies have modified kernels to control hardware resources. Additionally, an execution model has been proposed that can reduce interference by adjusting the execution order of tasks without software modification. Avionics systems require several rigorous software verification procedures. Therefore, modifying existing software can be costly and time-consuming. In this work, we propose a method to apply execution models proposed in existing studies without modifying commercial real-time operating systems. We implemented the time-division multiple access (TDMA) and acquisition execution restitution (AER) execution models with pseudo-partition and message queuing on VxWorks 653. Moreover, we propose a multi-TDMA model considering the characteristics of the target hardware. For the interference analysis, we measured the L1 and L2 cache misses and the number of main memory requests. We demonstrated that the interference caused by memory sharing was reduced by at least 60% in the execution model. In particular, multi-TDMA doubled utilization compared to TDMA and also reduced the execution time by 20% compared to the AER model.

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“…Puaut and Decotigny [4] explore the use of static cache locking of instruction caches in multitasking real-time systems, addressing both intra-task and inter-task interferences and leading better performance. Dugo et al proposed a method in [10]to mitigate interferences that occur in the memory hierarchy levels. Considering that predictability is a key concept of ARINC-653-compliant systems, their approach uses static cache locking.…”

Section: A Static Cache Lockingmentioning

confidence: 99%

A Dynamic Instruction Cache Locking Approach for Minimizing Worst Case Execution Time of a Single Task

et al. 2020

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In real time embedded system, the embedded software often consists of a set of concurrent tasks, and such tasks are generally subject to timing constraints. In order to satisfy all the timing constraints, precisely predicting the WCET of a task is essential for the task scheduler to construct a feasible schedule for a task set. Caches have been widely used to bridge the gap between high speed processors and relatively slower off-chip memory. However, caches make it extremely harder to predict precise WCET (Worst Case Execution Time ) of a task for the simple reason that it is difficult to predict if each cache access is a cache hit or miss. Cache locking is a mechanism which disables the replacement policy of caches and locks some contents (instruction or data) in the caches, such that the accesses to those contents become fully predictable and the WCET of a task is easier to predict. Furthermore, cache locking is also an effective technique to reduce the WCET of a task by locking appropriate contents in the caches. In this paper, we investigate the WCET-aware I-cache (Instruction cache) locking problem and propose an ILP-based (Integer Linear Programming) dynamic I-cache locking approach for reducing the WCET of a task. Our approach not only select locking contents which have largest benefit for reducing WCET of a task, but also finds a good locking point for each locked instruction such that extra execution time spend on locking instructions is also minimized. We have implemented this approach and compared it with two state-of-theart I-cache locking approaches, the longest path based dynamic cache locking approach proposed in and the min-cut based dynamic locking approach proposed in by using MRTC benchmark suite. The experimental results show that our approach performs better for each benchmark. Compared to the longest path based dynamic approach, our approach achieves the average improvements of 5.8%, 13.8%, 16.1% and 12.6% for the 256B, 512B, 1KB and 2KB caches, respectively. Compared to the min-cut based dynamic approach, our approach achieves the average improvements of 2.2%, 7.6%, 8.2% and 6.4% for the 256B, 512B, 1KB and 2KB caches, respectively.INDEX TERMS Cache locking, real-time systems, worst-case-executing-time.

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Cache Locking Content Selection Algorithms for ARINC-653 Compliant RTOS

Cited by 6 publications

References 15 publications

A Survey of Techniques for Reducing Interference in Real-Time Applications on Multicore Platforms

A Survey of Techniques for Reducing Interference in Real-Time Applications on Multicore Platforms

Execution Model to Reduce the Interference of Shared Memory in ARINC 653 Compliant Multicore RTOS

A Dynamic Instruction Cache Locking Approach for Minimizing Worst Case Execution Time of a Single Task

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