Cache operations by MRU change

So, Kimming; Rechtschaffen, R. N.

doi:10.1109/12.2208

Cited by 116 publications

(29 citation statements)

References 8 publications

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“…The NMRU (or non-MRU) replacement algorithm differentiates the most recently accessed (MRU) line from other lines in the set [41]. On a miss, a line is chosen (uniformly) randomly from among the A ′ − 1 non-MRU lines.…”

Section: Estimating φ φ φ(Nmru)mentioning

confidence: 99%

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Reuse-based online models for caches

Sen

Wood

2013

SIGMETRICS Perform. Eval. Rev.

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We develop a reuse distance/stack distance based analytical modeling framework for efficient, online prediction of cache performance for a range of cache configurations and replacement policies LRU, PLRU, RANDOM, NMRU. Our framework unifies existing cache miss rate prediction techniques such as Smith's associativity model, Poisson variants, and hardware way-counter based schemes. We also show how to adapt LRU way-counters to work when the number of sets in the cache changes. As an example application, we demonstrate how results from our models can be used to select, based on workload access characteristics, last-level cache configurations that aim to minimize energy-delay product.

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Section: Estimating φ φ φ(Nmru)mentioning

confidence: 99%

“…Partitioned LRU [41] (also popularly called pseudo-LRU) maintains a balanced binary tree that, at each level, differentiates between the two sub-trees based on access recency. Every internal node is represented by a single bit whose value decides which of the two subtrees was accessed more recently.…”

Section: Estimating φ φ φ(Plru)mentioning

confidence: 99%

Reuse-based online models for caches

Sen

Wood

2013

SIGMETRICS Perform. Eval. Rev.

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“…The wider CMP-SNUCA network provides the additional bandwidth needed by an 8-processor CMP, but requires longer latencies as compared to the originally proposed uniprocessor network. Fourth, shared CMP caches are subject to contention from different processors' working sets [32], motivating 16-way set-associative banks with a pseudo-LRU replacement policy [40]. Finally, we assume an idealized off-chip communication controller to provide consistent off-chip latency for all processors.…”

Section: Baseline Cmp Designmentioning

confidence: 99%

Managing Wire Delay in Large Chip-Multiprocessor Caches

Beckmann

Wood

37th International Symposium on Microarchitecture (MICRO-37'04)

276

275

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“…PLRU schemes employ approximations of the LRU mechanism to speed up operations and reduce the complexity of implementation [9], [10]. Due to the approximations, the least recently accessed cache memory is not always the location to be replaced.…”

Section: Common Cache Replacement Policiesmentioning

confidence: 99%

Performance evaluation of cache replacement policies for the SPEC CPU2000 benchmark suite

Al-Zoubi

Milenković

2004

Proceedings of the 42nd Annual Southeast Regional Conference

105

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Replacement policy, one of the key factors determining the effectiveness of a cache, becomes even more important with latest technological trends toward highly associative caches. The state-of-the-art processors employ various policies such as Random, Least Recently Used (LRU), Round-Robin, and PLRU (Pseudo LRU), indicating that there is no common wisdom about the best one. Optimal yet unattainable policy would replace cache memory block whose next reference is the farthest away in the future, among all memory blocks present in the set.In our quest for replacement policy as close to optimal as possible, we thoroughly explored the design space of existing replacement mechanisms using SimpleScalar toolset and SPEC CPU2000 benchmark suite, across wide range of cache sizes and organizations. In order to better understand the behavior of different policies, we introduced new measures, such as cumulative distribution of cache hits in the LRU stack. We also dynamically monitored the number of cache misses, per each 100000 instructions.Our results show that the PLRU techniques can approximate and even outperform LRU with much lower complexity, for a wide range of cache organizations. However, a relatively large gap between LRU and optimal replacement policy, of up to 50%, indicates that new research aimed to close the gap is necessary. The cumulative distribution of cache hits in the LRU stack indicates a very good potential for way prediction using LRU information, since the percentage of hits to the bottom of the LRU stack is relatively high.

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Cache operations by MRU change

Cited by 116 publications

References 8 publications

Reuse-based online models for caches

Reuse-based online models for caches

Managing Wire Delay in Large Chip-Multiprocessor Caches

Performance evaluation of cache replacement policies for the SPEC CPU2000 benchmark suite

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