Cache Persistence Analysis: Finally Exact

Stock, Gregory; Hahn, Sebastian; Reineke, Jan

doi:10.1109/rtss46320.2019.00049

Cited by 9 publications

(3 citation statements)

References 32 publications

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“…Cache hits take a single cycle, and misses take one look-up cycle plus the cycles required for a memory access. We consider a memory access time of 13 cycles both for instructions and data, which is a realistic value for main memories such as the Automotive DRAM MT46V16M16 [22] clocked at 100 MHz, and has been used in previous studies [16], [23]. For the ACDC, accesses that replace a dirty cache line take a total of 27 cycles to look-up (1), write back the dirty line to memory (13), and bring in the new line from memory (13).…”

Section: Experimental Environmentmentioning

confidence: 99%

Improving the Configuration of the Predictable ACDC Data Cache for Real-Time Systems

Segarra

Campoy²

2022

IEEE Access

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In real-time systems, analyzing the worst-case execution time (WCET) of a task in the presence of data caches is hard. The ACDC is a data cache that provides predictability, facilitating WCET analysis. It works by granting data cache replacement permission to specific load/store instructions. Nonetheless, knowing how to select these instructions to minimize the WCET, i.e., configuring the ACDC, is not trivial. In this paper, we propose four new methods to configure the ACDC, and compare them with existing methods. Unlike those in previous studies, our proposed methods provide specific ACDC configurations for the different phases of a given task, instead of a single ACDC configuration per task. We evaluate the WCET bounds obtained when using different ACDC configuration methods on the TACLeBench benchmark suite. Our results show that the most complex benchmarks work better with multiple-content configurations, which indicates that realistic tasks may also benefit from this kind of configuration. The methods proposed in this study improve the WCET in more than 60% of cases, with an average WCET improvement of nearly 5% and up to 50% in some cases.INDEX TERMS ACDC, WCET, data cache, real-time, genetic algorithms, static analysis.

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Section: Experimental Environmentmentioning

confidence: 99%

Improving the Configuration of the Predictable ACDC Data Cache for Real-Time Systems

Segarra

Campoy²

2022

IEEE Access

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“…The ability to predict such accesses correctly thus determines the accuracy of timing analyses. Especially data caches are, however, highly unpredictable [20], which gave rise to a wide field of research [21] still actively worked on today [22]. The problem is aggravated through inter-core interferences in multi-core shared-memory environments [23].…”

Section: Background and Related Workmentioning

confidence: 99%

Migration-Based Synchronization

Raffeck

Gerhorst

Schröder-Preikschat

et al. 2021

2021 XI Brazilian Symposium on Computing Systems Engineering (SBESC)

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A fundamental challenge in multi-and many-core systems is the correct execution of concurrent access to shared data. A common drawback from existing synchronization mechanisms is the loss of data locality as the shared data is transferred between the accessing cores. In real-time systems, this is especially important as knowledge about data access times is crucial to establish bounds on execution times and guarantee the meeting of deadlines.We propose in this paper a refinement of our previously sketched approach of Migration-Based Synchronization (MBS) as well as its first practical implementation. The core concept of MBS is the replacement of data migration with controlflow migration to achieve synchronized memory accesses with guaranteed data locality. This leads to both shorter and more predictable execution times for critical sections. As MBS can be used as a substitute for classical locks, it can be employed in legacy applications without code alterations.We further examine how the gained data locality improves the results of worst-case timing analyses and results in tighter bounds on execution and response time. We reason about the similarity of MBS to existing synchronization approaches and how it enables us to reuse existing analysis techniques.Finally, we evaluate our prototype implementation, showing that MBS can exploit data locality with similar overheads as traditional locking mechanisms.

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“…This simplifies the analysis, but conventional caches usually follow the opposite approach, namely, writeallocate with fetch on write-miss and copyback, which results in fewer memory transfers in general [17]. A recent study on must/may analysis also improves its precision, but it does not consider copybacks either [28]. Moreover, all these previous approaches are based on tracking the specific value of memory addresses, whereas our proposal represents accesses as expressions and abstract relations, so that reuse is marked when it can be asserted that two data references access the same memory address, independently of whether the address is known or unknown.…”

Section: Related Workmentioning

confidence: 99%

Automatic Safe Data Reuse Detection for the WCET Analysis of Systems With Data Caches

et al. 2020

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Worst-case execution time (WCET) analysis of systems with data caches is one of the key challenges in real-time systems. Caches exploit the inherent reuse properties of programs, temporarily storing certain memory contents near the processor, in order that further accesses to such contents do not require costly memory transfers. Current worst-case data cache analysis methods focus on specific cache organizations (LRU, locked, ACDC, etc.). In this paper, we analyze data reuse (in the worst case) as a property of the program, and thus independent of the data cache. Our analysis method uses Abstract Interpretation on the compiled program to extract, for each static load/store instruction, a linear expression for the address pattern of its data accesses, according to the Loop Nest Data Reuse Theory. Each data access expression is compared to that of prior (dominant) memory instructions to verify whether it presents a guaranteed reuse. Our proposal manages references to scalars, arrays, and non-linear accesses, provides both temporal and spatial reuse information, and does not require the exploration of explicit data access sequences. As a proof of concept we analyze the TACLeBench benchmark suite, showing that most loads/stores present data reuse, and how compiler optimizations affect it. Using a simple hit/miss estimation on our reuse results, the time devoted to data accesses in the worst case is reduced to 27% compared to an always-miss system, equivalent to a data hit ratio of 81%. With compiler optimization, such time is reduced to 6.5%.

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Cache Persistence Analysis: Finally Exact

Cited by 9 publications

References 32 publications

Improving the Configuration of the Predictable ACDC Data Cache for Real-Time Systems

Improving the Configuration of the Predictable ACDC Data Cache for Real-Time Systems

Migration-Based Synchronization

Automatic Safe Data Reuse Detection for the WCET Analysis of Systems With Data Caches

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