Cache Sharing Management for Performance Fairness in Chip Multiprocessors

Zhou, Xing; Chen, Wenguang; Zheng, Weimin

doi:10.1109/pact.2009.40

Cited by 25 publications

(21 citation statements)

References 17 publications

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“…Mutlu et al [6] propose a shared DRAM controller, with the aim of both improve program's performance and the QoS of programs. Zhou et al [7] introduces a model to analyze the perfor-mance impact of cache sharing, and proposes a mechanism of cache sharing management to provide performance fairness for concurrently executing applications.…”

Section: Related Workmentioning

confidence: 99%

Ensuring the Fairness of program’s performance on CMP

Wang¹,

Gao²,

Hou³

et al. 2017

MATEC Web Conf.

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Abstract. On CMP, programs commonly interference with each other. But for programs co-running on CMP, serious performance dropdown is not expected. With the growth of the program's size, program's contention for limited shared resources in the system will become increasingly intense, and the resulting impact on system performance will be even more pronounced. How to allocate and share limited shared resources among programs is a very important problem. In this paper we propose a new method to ensure the fairness of program's performance on CMP. The share resource CPU and memory are included in our study. Meanwhile, the Linux resource management tool Cgroups is used to realize our idea. By the resource we profiled and the tool support, we realize a reasonable resource dividing method to ensure the fairness of program's performance. The reasonable resource dividing method include three Engine. The experiment result show that making use of the fairness resource dividing method proposed by our paper, compared with operating system scheduling, program's performance difference can be largely reduced.

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Section: Related Workmentioning

confidence: 99%

Ensuring the Fairness of program’s performance on CMP

Wang¹,

Gao²,

Hou³

et al. 2017

MATEC Web Conf.

View full text Add to dashboard Cite

show abstract

“…A limitation of this mechanism is that it needs to know for every miss whether it is an inter-thread miss or intra-thread miss, which incurs significant hardware overhead. Zhou et al [2009] propose a complex set of counters to estimate the performance impact of inter-thread misses. Its accuracy quickly drops when sampling is employed though.…”

Section: Quantifying Impact Of Cache Sharingmentioning

confidence: 99%

“…A large body of recent work has focused on cache partitioning in multicore processors, see for example ;Iyer [2004], Iyer et al [2007], Jaleel et al [2008], Kim et al [2004], Nesbit et al [2007], Qureshi and Patt [2006], and Zhou et al [2009]. These proposals did not quantify per-thread progress, but aimed at improving multicore throughput while guaranteeing some level of fairness among coexecuting jobs.…”

Section: Cache Partitioningmentioning

confidence: 99%

Per-thread cycle accounting in multicore processors

Bois

Eyerman

Eeckhout

2013

ACM Trans. Archit. Code Optim.

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While multicore processors improve overall chip throughput and hardware utilization, resource sharing among the cores leads to unpredictable performance for the individual threads running on a multicore processor. Unpredictable per-thread performance becomes a problem when considered in the context of multicore scheduling: system software assumes that all threads make equal progress, however, this is not what the hardware provides. This may lead to problems at the system level such as missed deadlines, reduced quality-of-service, non-satisfied service-level agreements, unbalanced parallel performance, priority inversion, unpredictable interactive performance, etc.This article proposes a hardware-efficient per-thread cycle accounting architecture for multicore processors. The counter architecture tracks per-thread progress in a multicore processor, detects how inter-thread interference affects per-thread performance, and predicts the execution time for each thread if run in isolation. The counter architecture captures the effects of additional conflict misses due to cache sharing as well as increased latency for other memory accesses due to resource and bandwidth contention in the memory subsystem. The proposed method accounts for 74.3% of the interference cycles, and estimates per-thread progress within 14.2% on average across a large set of multi-program workloads. Hardware cost is limited to 7.44KB for an 8-core processor, a reduction by almost 10× compared to prior work while being 63.8% more accurate. Making system software progress aware improves fairness by 22.5% on average over progressagnostic scheduling.

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“…Several groups have been proposing schemes for per-thread cycle accounting, see for example [5,7,8,12,13,16]. All of the proposals focused on multi-program workloads of independent single-threaded applications, and none focused on multi-threaded applications involving the performance impact of positive interference and spinning/yielding.…”

Section: Related Workmentioning

confidence: 99%

Speedup stacks: Identifying scaling bottlenecks in multi-threaded applications

Eyerman

Bois

Eeckhout

2012

2012 IEEE International Symposium on Performance Analysis of Systems &Amp; Software

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Multi-threaded workloads typically show sublinear speedup on multi-core hardware, i.e., the achieved speedup is not proportional to the number of cores and threads. Sublinear scaling may have multiple causes, such as poorly scalable synchronization leading to spinning and/or yielding, and interference in shared resources such as the lastlevel cache (LLC) as well as the main memory subsystem. It is vital for programmers and processor designers to understand scaling bottlenecks in existing and emerging workloads in order to optimize application performance and design future hardware.In this paper, we propose the speedup stack, which quantifies the impact of the various scaling delimiters on multithreaded application speedup in a single stack. We describe a mechanism for computing speedup stacks on a multi-core processor, and we find speedup stacks to be accurate within 5.1% on average for sixteen-threaded applications. We present several use cases: we discuss how speedup stacks can be used to identify scaling bottlenecks, classify benchmarks, optimize performance, and understand LLC performance.

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Cache Sharing Management for Performance Fairness in Chip Multiprocessors

Abstract: Resource sharing can cause unfair and unpredictable performance of concurrently executing applications in Chip-Multiprocessors (CMP

Cited by 25 publications

References 17 publications

Ensuring the Fairness of program’s performance on CMP

Ensuring the Fairness of program’s performance on CMP

Per-thread cycle accounting in multicore processors

Speedup stacks: Identifying scaling bottlenecks in multi-threaded applications

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