Cad and routing architecture for interposer-based multi-FPGA systems

Abstract

Interposer-based multi-FPGA systems are composed of multiple FPGA dice connected through a silicon interposer. Such devices allow larger FPGA systems to be built than one monolithic die can accomodate and are now commercially available. An open question, however, is how efficient such systems are compared to a monolithic FPGA, as the number of signals passing between dice is reduced and the signal delay between dice is increased in an interposer system vs. a monolithic FPGA.We create a new version of VPR to investigate the architecture of such systems, and show that by modifying the placement cost function to minimize the number of signals that must cross between dice we can reduce routing demand by 18% and delay by 2%. We also show that the signal count between dice and the signal delay between dice are key architecture parameters for interposer-based FPGA systems. We find that if an interposer supplies (between dice) 60% of the routing capacity that the normal (within-die) FPGA routing channels supply, there is little impact on the routability of circuits. Smaller routing capacities in the interposer do impact routability however: minimum channel width increases by 20% and 50% when an interposer supplies only 40% and 30% of the within-die routing, respectively. The interposer also impacts delay, increasing circuit delay by 34% on average for a 1 ns interposer signal delay and a four-die system. Reducing the interposer delay has a greater benefit in improving circuit speed than does reducing the number of dice in the system.

Effects of I/O routing through column interfaces in embedded FPGA fabrics

“…Several recent papers have examined the effects of limited 2.5D interconnect using interposers. It was found that limited I/O interconnect can make design placement more difficult, impacting design performance [8]. More recent 2.5D FPGAs [2] address this issue by including clusters of flip flops in interface blocks on the FPGA die close to the interposer boundary (Laguna tiles).…”

Three-dimensional Mesh of Clusters: An alternative unified high performance interconnect architecture for 3D-FPGA implementation

“…The 2.5D multi-FPGA silicon integration is able to improve the manufacturing of high density FPGA, however failed to improve the performance of the FPGA chip [7]. In this paper, we propose a 2.5D and 3D interconnect network implementation based on a MoC topology for the implementation of an efficient FPGA architecture design.…”

Design automation flow for partial run-time reconfiguration on FPGAs

“…Recently, interposer-based FPGAs are proposed to significantly improve the logic capacity, interconnection bandwidth and performance [HPB14]. For instance, Xilinx Inc., a major FPGA vendor, firstly developed the largest interposer-based FPGA, the Virtex-7…”

“…XC7V2000T, which has 4 dies and 1.95 million logic elements [HPB14]. A general twoand-a-half-dimensional (2.5D) FPGA with interposer is shown in Fig.…”

“…5.1 [HPB14], where four FPGA dies are placed vertically and are connected by the interposer. The interposer is an electric interface routing for connecting different components and can be used to spread connections, e.g., providing alternative routes for a connection [HPB14]. In order to connect between different dies, the signal needs to go through the internal track of the current die, microbump, and super long line (SLL) of interposer, and then into the other die.…”