Calculating the effective capacitance for the RC interconnect in VDSM technologies

Abbaspour, Soroush; Pedram, Massoud

doi:10.1145/1119772.1119781

Cited by 15 publications

(10 citation statements)

References 13 publications

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“…Typically, the effective capacitance stores the same amount of charge as the RC-π load until a certain point of the output voltage transition [11][12] [13] (e.g., the 50% point of the output transition.) Figure 3(a) depicts a typical CMOS driver with its input waveform and RC-π load.…”

Section: A New Approach For Effective Capacitance Calculation In Statmentioning

confidence: 99%

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Parameterized block-based non-gaussian statistical gate timing analysis

Abbaspour

Fatemi

Pedram

2006

Proceedings of the 2006 Conference on Asia South Pacific Design Automation - ASP-DAC '06

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Section: A New Approach For Effective Capacitance Calculation In Statmentioning

confidence: 99%

“…(12) is the iterative c eff calculation under the nominal conditions of the circuit. Hence, c eff,0 can be evaluated by using the conventional effective capacitance calculation [12] [13].…”

Section: E C F T T C C R Cmentioning

confidence: 99%

Parameterized block-based non-gaussian statistical gate timing analysis

Abbaspour

Fatemi

Pedram

2006

Proceedings of the 2006 Conference on Asia South Pacific Design Automation - ASP-DAC '06

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“…Using the sum of all load capacitances as the capacitive load is simple, but can be quite pessimistic [16]. A more accurate approximation for an n th order load seen by the gate (i.e., a load with n distributed capacitances to ground) is to use a second order RC-π model [8].…”

Section: Introductionmentioning

confidence: 99%

“…A more accurate approximation for an n th order load seen by the gate (i.e., a load with n distributed capacitances to ground) is to use a second order RC-π model [8]. Therefore, the "effective capacitance" approach has been proposed [9][14] [16] whereby the RC-π load is approximated by an equivalent capacitance, Ceff. All of effective capacitance approaches resort to the iterative calculation of Ceff for the given circuit scenario, which can be costly in the context of physical design optimization tools.…”

Section: Introductionmentioning

confidence: 99%

Fast Interconnect and Gate Timing Analysis for Performance Optimization

Abbaspour

Pedram

Ajami

et al. 2006

IEEE Trans. VLSI Syst.

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Static timing analysis (STA) is a key step in the physical design optimization of VLSI designs. The lumped capacitance model for gate delay and the Elmore model for wire delay have been shown to be inadequate for wire-dominated designs. Using the effective capacitance model for the gate delay calculation and model order reduction techniques for wire delay calculation is prohibitively expensive. In this paper, we present sufficiently accurate and highly efficient filtering algorithms for interconnect timing as well as gate timing analysis. The key idea is to partition the circuit into low and high complexity circuits, whereby low complexity circuits are handled with efficient algorithms such as total capacitance algorithm for gate delay and the Elmore metric for wire delay and high complexity circuits are handled with sign-off algorithms. Experimental results on microprocessor designs show accuracies that are quite comparable with sign-off delay calculators with more than of 65% reduction in the computation times.

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“…A more accurate approximation for an n th order load seen by the gate/cell (i.e., a load with n distributed capacitances to ground) is to use a second order RC-π  model [3,5]. Equating the first, second, and third moments of the admittance of the real load with the first, second, and third moments of the RC-π load [19], we can find C1, Rπ, and C2 as shown in Figure 3. It follows that for accurate gate delay calculation, we can use a four-dimensional delay table, where the dimensions are Tin, C1, Rπ, and C2.…”

Section: Return Tαmentioning

confidence: 99%