Calibrating clock stretch during AC scan testing

Rearick, Jeff; Rodgers, Richard W.

doi:10.1109/test.2005.1583984

Cited by 56 publications

(20 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…These reordered sequences sets are obtained in four ways: 5 , T 8 ; (iv) the descending order of output deviations. In the deviation-based method, test sequences with higher deviations are ranked first.…”

Section: Table IV Rt-level Deviations Of Ten Functional Tests For Schmentioning

confidence: 99%

Functional Test-Sequence Grading at Register-Transfer Level

Fang

Chakrabarty

Jas

et al. 2012

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

Abstract-Functional test sequences are often used in manufacturing testing to target defects that are not detected by structural test. Therefore, it is necessary to evaluate the quality of functional test sequences. However, it is very time-consuming to evaluate the quality of functional test sequences by gate-level fault simulation. Therefore, we propose output deviations as a surrogate metric to grade functional test sequences at the register transfer (RT)-level without explicit fault simulation. Experimental results for the open-source Biquad filter core and the Scheduler module of the Illinois Verilog Model (IVM) show that the deviations metric is computationally efficient and it correlates well with gatelevel coverage for stuck-at, transition-delay and bridging faults. Results also show that functional test sequences reordered based on output deviations provide steeper gate-level fault coverage ramp-up compared to other ordering methods.

show abstract

Section: Table IV Rt-level Deviations Of Ten Functional Tests For Schmentioning

confidence: 99%

Functional Test-Sequence Grading at Register-Transfer Level

Fang

Chakrabarty

Jas

et al. 2012

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

show abstract

“…On the other hand, as the small delay defects become one of dominant defect types introduced during manufacture due to the process variation, at-speed test set based on transition fault model become mandatory to be included in the test suites in order to achieve adequate test quality. It has been shown that IR drop issues caused by the excessive test power consumption reduce the effectiveness of at-speed scan testing, resulting test escape due to clock stretch [6], and yield loss due to incorrect capture caused by additional gate delay [7]. Test power reduction in the scan based tests has become more urgent in today's nanometer designs.…”

Section: Open Accessmentioning

confidence: 99%

Low Power Testing—What Can Commercial Design-for-Test Tools Provide?

Lin

2011

JLPEA

View full text Add to dashboard Cite

show abstract

“…The authors in [14] showed a case study of the effects of IR-drop and explored quiet pattern (reduced transition) generation methods to reduce it. Recently, the effects of power supply noise on clock frequency during delay test was presented in [15].…”

Section: Related Prior Workmentioning

confidence: 99%