Calibrating sample and hold stages with pruned Volterra kernels

Abstract

Switched capacitor sample and hold (SHA) stages in deep submicron technologies can achieve hundreds of mega samples per second of sampling frequency, but are affected by several nonlinear effects which reduce their signal-to-noise-and-distortion ratio (SNDR): CMOS switch non-idealities, amplifier nonlinearity, and incomplete settling. It is possible to model and correct distortions using Volterra kernels, which can be rather resource-consuming as the number of parameters to estimate rapid increases with the order and length of the kernels. In this reported work, it is shown that a switched capacitor SHA, simulated using the 45 nm process by STMicroelectronics, can be calibrated to achieve a 10-24 dB improvement in SNDR. Computational costs are kept low using a different lag value for each kernel, and iteratively pruning the elements of the Volterra kernels which affect linearity the least. A technique for estimation and outof-sample validation is presented and robustness checks are performed. A performance gain of 8.5 dB can be achieved with as few as 17 correction parameters, while 21 coefficients are enough to gain 12.2 dB, and 36 to gain 18.4 dB.Introduction: Sample and hold (SHA) stages are the front-end of most ADCs and can be a limiting factor for the linearity of the overall system, especially at high sampling frequencies.Volterra kernels [1] can be used to improve the linearity of mixedsignal circuits (such as SHA stages). However, the number of parameters to be estimated can be large, thus increasing the computational cost. Subsets of Volterra kernels with a reduced number of parameters can be used to model specific nonlinearities; for instance, the nonlinear switch on-resistance [2, 3]. Nikaeen and Murmann [2] achieved a performance improvement of more than 20 dB using hundreds of coefficients, whereas without complexity reduction the number of parameters would have run into thousands. Satarzadeh et al.[3] developed a model which reduces complexity (to tens of parameters) with a linearity improvement of about 10 dB, up to close to 30 dB for larger models and using inherently more linear analogue circuit techniques such as bootstrap switches. These techniques are tailored for a specific model of distortion and may thus be less effective in a more general case in which switch nonlinearities, amplifier nonlinearities, and incomplete signal settlings are present, which is often the case in low-power high-speed SHA stages. Satarzadeh et al.[3] also showed that some circuit techniques can be less amenable to calibration, as switches implemented using transmission gates achieve lower linearity improvement.In this Letter, we show that Volterra kernels of limited complexity (short memory) which use a specific lag for each order of nonlinearity, after careful pruning of the model to eliminate the parameters which add little to overall performance, achieve robust performance improvement. Fig. 1 shows the architecture of a calibrated system: the output Out of an SHA is fed to a digital block (called Correction) whi...

Calibration of pipeline ADC with pruned Volterra kernels

“…Introduction: Non-linear calibration of pipeline ADCs enables better linearity and higher sampling frequency, correcting errors due to incomplete settling, slew-rate limitations, switches' and amplifiers' nonlinearity, and so on. Calibration using Volterra models with iterative pruning, presented in [1] for a sample and hold (SHA) stage, can be extended to pipeline ADCs, and its performance advantage increases with the sampling frequency of the ADC. This approach achieves better linearity with comparable complexity than other simplified Volterra models found in the literature.…”

“…Volterra models [2] are meant for weakly non-linear effects. For this reason ADC front-end stages, such as SHAs [1,3,4], can be more accurately represented with Volterra models, as they do not contain comparators, which produce heavily non-linear behaviour. More complex models can be expected to be required in ADCs.…”

“…Model complexity is a limiting factor in the applicability of Volterra models. An a posteriori approach to reduce the computational complexity of Volterra models was applied in [1] to a SHA stage. For each kernel order, a specific memory length was chosen, and an iterative pruning technique was then used to further reduce complexity.…”

“…To reduce model complexity, as in [1], the length of each kernel falls with the kernel order; besides, even-order kernels are neglected or made shorter because of the fully-differential architecture; finally, iterative pruning is applied to minimise complexity.…”

“…In [4], a simplified Volterra model was obtained by forcing h o i1,i2,...,io = 0 for i 2 , i 3 , …, i o ≠ 0 in (1). This model is also used in [9], though in the frequency domain, as described in Subsection III.A in that paper.…”