Calibration and Dynamic Matching in Data Converters: Part 1: Linearity Calibration and Dynamic-Matching Techniques

Dyer, K.C.; Keane, John; Lewis, S.H.

doi:10.1109/mssc.2017.2771106

Cited by 12 publications

(6 citation statements)

References 30 publications

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“…Besides random errors, i. e. thermal and quantization noise, digital-to-analog converter (DAC) or gain mismatches cause systematic errors. To maintain a high linearity, calibration techniques for these systematic errors become inevitable and were heavily investigated throughout the past decades [2], [3]. To reduce power consumption and relax the analog design, calibration techniques are preferably carried out in the digital domain [4].…”

Section: Introductionmentioning

confidence: 99%

“…A closer look at the principle of [16] shows that in this sense, it relies on a weak form of additivity, where the constant voltageoffset replaces the second input signal y in (2).…”

Section: Introductionmentioning

confidence: 99%

“…In this work, always the parameter corresponding to the lowest stage output level is excluded 2. Every output level providing x s,i ̸ = 0 may be utilized for the replacement.…”

mentioning

confidence: 99%

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Homogeneity Enforced Calibration of Stage Nonidealities for Pipelined ADCs

Bauernfeind

Huemer

2023

IEEE Trans. Circuits Syst. II

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Pipelined analog-to-digital converters (ADCs) are fundamental components of various signal processing systems requiring high sampling rates and a high linearity. Over the past years, calibration techniques have been intensively investigated to increase the linearity. In this work, we propose an equalization-based calibration technique which does not require knowledge of the ADC input signal for calibration. For that, a test signal and a scaled version of it are fed into the ADC sequentially, while only the corresponding output samples are used for calibration. Several test signal sources are possible, such as a signal generator (SG) or the system application (SA) itself. For the latter case, the presented method corresponds to a background calibration technique. Thus, slowly changing errors are tracked and calibrated continuously. Because of the low computational complexity of the calibration technique, it is suitable for an onchip implementation. Ultimately, this work contains an analysis of the stability and convergence behavior as well as simulation results.

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Section: Introductionmentioning

confidence: 99%

“…A closer look at the principle of [16] shows that in this sense, it relies on a weak form of additivity, where the constant voltageoffset replaces the second input signal y in (2).…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Homogeneity Enforced Calibration of Stage Nonidealities for Pipelined ADCs

Bauernfeind

Huemer

2023

IEEE Trans. Circuits Syst. II

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“…Laser trimming requires a laser and thin-film process, which raises the complexity of fabrication and packaging. The laser also suffers from drifting issue [18]. As for fuse trimming, probe pads often limit the efficacy of calibration.…”

Section: Introductionmentioning

confidence: 99%

Memristor-Assisted Background Calibration for SAR ADCs: A Feasibility Study

Wang

Jiang

et al. 2023

IEEE Trans. Circuits Syst. I

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This paper proposes a memristor-assisted sign-based background calibration scheme for analog-to-digital converters (ADCs). The scheme was implemented and validated in a 12bit asynchronous successive approximation register (SAR) ADC, which consists of a hybrid binary weighted/R-2R digital-to-analog converter (binary/R-2R DAC) and other peripheral circuits. This hybrid DAC, in which one redundancy bit is introduced, is built with a memristor and standard polysilicon resistors. The proposed calibration technique can detect the errors caused by DAC mismatches and correct them by adjusting the resistance of the memristor (memristance 1 ) in a feedback loop. The implemented circuit takes the memristor's advantages such as small area and resistance switching property. The proposed scheme has been designed and simulated in a standard 180 nm CMOS process. Eventually, a monolithic CMOS/memristor chip will be fabricated with the CMOS part processed at a standard foundry and the memristors integrated through post-CMOS processing in house. Simulation results demonstrate the feasibility of exploiting memristors to improve the linearity of high-resolution SAR ADCs. The designed calibration scheme can effectively reduce the integral non-linearity (INL) and differential non-linearity (DNL) of the 12-bit SAR ADC.

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“…The delay between the feedback DAC and quantiser can be minimised with the help of low-latency DEM. Also, fixed delay between the feedback DAC and the quantiser can be compensated using the straight feedback path to the quantiser [13]. On the other hand, a highly efficient DEM method namely, data weighted averaging (DWA) is specifically used when the feedback path contains several DAC components [14].…”

Section: Introductionmentioning

confidence: 99%

Efficient CTDSM based on GM‐C quantiser and improved dynamic element matching

Sahu¹,

Chandra

Sinha

et al. 2020

IET Circuits, Devices & Systems

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In this study, a continuous-time delta-sigma modulator (CTDSM) is developed using a Gm-C based noise-shaping quantiser (Gm-C-NSQ) with an improved dynamic element matching (i-DEM) algorithm. Here, a Gm-C integrator is used to develop NSQ, since it increases the effectiveness of the proposed modulator in terms of power consumption and die area. This Gm-C-NSQ uses only three dynamic latches to provide efficient quantisation level and to increase the order of noise shaping. Moreover, an i-DEM algorithm is utilised to reduce the non-linearities of the quantiser and mismatching error of the digital-toanalogue converters presented in the feedback structure of the modulator. Here, an 180 nm CMOS technology is used to design the proposed modulator and it functions at 2.6 MHz sampling frequency. Simulation results show that the proposed modulator can achieve a peak spurious-free dynamic range (SFDR) of 93.67 dB and a peak signal-to-noise ratio of 87.38 dB for 20 kHz signal bandwidth. Furthermore, the proposed modulator consumes 0.0863 mW power when 1.2 V supply voltage is applied.

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Calibration and Dynamic Matching in Data Converters: Part 1: Linearity Calibration and Dynamic-Matching Techniques

Cited by 12 publications

References 30 publications

Homogeneity Enforced Calibration of Stage Nonidealities for Pipelined ADCs

Homogeneity Enforced Calibration of Stage Nonidealities for Pipelined ADCs

Memristor-Assisted Background Calibration for SAR ADCs: A Feasibility Study

Efficient CTDSM based on GM‐C quantiser and improved dynamic element matching

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