Calibration-less Nauta OTA operating at 0.25-V power supply in a 130-nm digital CMOS process

Braga, Rodrigo Aparecido da Silva; Ferreira, Luís H. C.; Colletta, Gustavo Della; Dutra, Odilon O.

doi:10.1109/lascas.2017.7948039

Cited by 7 publications

(9 citation statements)

References 12 publications

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“…This current charges the inverter up to operate at its threshold voltage, V SP [9]. Since a single inverter works as an amplifier when biased around the point V i = V o [8], we calculate I SC for V SP = V DD /2, according to: Note that we can establish the threshold voltage by choosing appropriate transistor geometries and also design the I SC current [10]. In addition, from Figure 3, the output current is calculated as I o = I p − I n , and by invoking (4), we have:…”

Section: Transconductance Of the Cmos Invertermentioning

confidence: 99%

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A Fully Differential Difference Transconductance Amplifier Topology Based on CMOS Inverters

et al. 2023

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This manuscript presents a fully differential difference transconductance amplifier (FDDTA) architecture based on CMOS inverters. Designed in a 130-nm CMOS process it operates in weak inversion when supplied with 0.25 V. In addition, the FDDTA requires no supplementary external calibration circuit, like tail current or bias voltage sources, since it relies on the distributed layout technique that intrinsically matches the CMOS inverters. For analytical purposes, we carried out a detailed investigation that describes all the concepts and the whole operation of the FDDTA architecture. Furthermore, a comparison between the modeling equations and measured data assures high performance.

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Section: Transconductance Of the Cmos Invertermentioning

confidence: 99%

“…In our previous work, we studied the topology of Nauta OTA [9] adapted to operate in ultra-low power and low displacement voltage, using arrays of halo-implanted transistors [10]. Based on this work, we developed an FDDTA that was used in a fifth-order Butterworth low-pass filter [11].…”

Section: Introductionmentioning

confidence: 99%

A Fully Differential Difference Transconductance Amplifier Topology Based on CMOS Inverters

et al. 2023

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“…Em (R. A. Braga, Ferreira, Colletta, & Dutra, 2017;R. A. Braga, Ferreira, Colletta, & Dutra, 2019) é apresentado uma implementação para o amplificador operacional de transcondutância fully diferencial baseado em inversores CMOS construídos com transistores MOS matriciais haloimplantados em um processo CMOS de 130 nm.…”

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Projeto de um OTA Baseado em Inversores em Processo CMOS de 130 nm

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Braga

Karolak

et al. 2020

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In manufacturing processes of integrated differential amplifiers, an inherent characteristic is that the fabricated nMOS and pMOS transistors have physical differences in relation to the projected values, an effect known as mismatch. In this work, the manufacturing process variations in operational transconductance amplifiers (OTA) are evaluated. Two OTA based on CMOS inverters are designed using both low threshold and standard threshold uniformly doped transistors using quantitative experimental research.

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“…In Braga et al (2017) a design strategy using the series-parallel transistor association (GALUP-MONTORO; SCHNEIDER; LOSS, 1994) is proposed to compensate for the mismatch variability and the effects of the Halo implantation on the inverter-based Nauta OTA. As the series association increases the equivalent transistor channel length, the process variability and the Halo implantation effects are reduced.…”

Section: Compensation Of the Pvt Variation On The Ulv Amplifiersmentioning

confidence: 99%

“…33, to adjust the W value to the fabrication process grid and the use of multipliers and multifingers when high W/L aspect ratio transistors are needed. Further, a step is added to the function to allow the design using series-parallel transistor association (GALUP-MONTORO; SCHNEIDER; LOSS, 1994) that is a very important design strategy for low-frequency (Kilo-Hertz range) ULV circuits (FERREIRA et al, 2014;BRAGA et al, 2017) but it was not employed in this work due to the operation in higher frequencies (Mega-Hertz range). A variation of the algorithm depicted in Fig.…”

Section: Proposed Operation-point Simulation-based Design Toolmentioning

confidence: 99%

Filtros RC-Ativo ULV e ULP combinando OTA de único estágio e transcondutância negativa de entrada para receptores RF de baixa energia.

Severo¹

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I would like to thanks to Professor Wilhelmus Adrianus Maria Van Noije for the opportunity in work as a Ph.D. candidate at the Polytechnic School of the University of São Paulo and by all the challenges imposed to me that have collaborated significantly in the improvements of my professional abilities. I would like to thanks to the Federal University of Pampa for the opportunity of being on leave from the university by 3.5 years that made possible working full time in the Ph.D. studies and to the CNPq research agency for support to this work. I would also like to thanks to professors João A. Martino e Paula G. Der Agopian for all the help in the CMOS transistor characterization, to the IMEC Free-mini@asic and to the MOSIS Educational programs for the free integrated circuit fabrications and to professors João N. Soares Júnior and Márcio C. Schneider for all the suggestions gave me at the qualification exam. I would like to thanks to all the members of the DMPSV department of the LSI at USP, especially to Silvana, for all the conversations at the coffee time and commemoration during my stay in São Paulo. Finally, I thanks to my wife Tanísia for all the help and understanding during this shortage of time phase of my life.

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Calibration-less Nauta OTA operating at 0.25-V power supply in a 130-nm digital CMOS process

Cited by 7 publications

References 12 publications

A Fully Differential Difference Transconductance Amplifier Topology Based on CMOS Inverters

A Fully Differential Difference Transconductance Amplifier Topology Based on CMOS Inverters

Projeto de um OTA Baseado em Inversores em Processo CMOS de 130 nm

Filtros RC-Ativo ULV e ULP combinando OTA de único estágio e transcondutância negativa de entrada para receptores RF de baixa energia.

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