Calibration of OPC models for multiple focus conditions

Schacht, Jochen; Herold, Klaus; Zimmermann, Rainer; Torres, J. Andres; Maurer, Wilhelm; Granik, Yuri; Chang, Ching-Hsu; Hung, George K.; Lin, B. N.

doi:10.1117/12.534123

Cited by 12 publications

(9 citation statements)

References 5 publications

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“…For example, the focus parameter of the optical image has been arbitrarily mixed with other photoresist blurring effects leading to poor separation of optical and photoresist models. 5 Similar coupling is seen between the mask and the photoresist models. 6 If a mask making process has systematic effects that occur on a length scale consistent with the optical interaction range, and these effects are ignored in the OPC modeling, then these are accounted for in the photoresist model.…”

Section: Introductionsupporting

confidence: 62%

Through-process modeling in a DfM environment

Mansfield¹,

Han²,

Al-Imam

et al. 2006

SPIE Proceedings

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In recent years, design for manufacturability (DfM) has become an important focus item of the semiconductor industry and many new DfM applications have arisen. Most of these applications rely heavily on the ability to model process sensitivity and here we explore the role of through-process modeling on DfM applications. Several different DfM applications are examined and their lithography model requirements analyzed. The complexities of creating through-process models are then explored and methods to ensure their accuracy presented.

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Section: Introductionsupporting

confidence: 62%

Through-process modeling in a DfM environment

Mansfield¹,

Han²,

Al-Imam

et al. 2006

SPIE Proceedings

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“…This flow provides more convenient calibration than one that rely on separate optical and process model calibrations. 6 Notice that the choice of the NC is rather arbitrary. As long as a FE condition is chosen as nominal, all other conditions are considered relative to the NC in terms of the focus and exposure difference ∆f and ∆d.…”

Section: Fem Modelmentioning

confidence: 99%

“…Notice that this formulism also covers the commonly used threshold models. 6 For simplicity we consider a thin-mask model where we exclude the mask topography and mask-induced polarization effects. However the methodology described in this paper applies to thick mask models as well.…”

Section: Lithography Process Modelingmentioning

confidence: 99%

A focus exposure matrix model for full chip lithography manufacturability check and optical proximity correction

Zhang¹,

Mu²,

Liu³

2006

SPIE Proceedings

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Due to the low k 1 -factor which leads to reduced process latitude, it is becoming increasingly important that OPC and lithography verification take into account process variations. An essential element to the successful implementation of full-chip, process window aware RET/OPC design and verification is a lithography model that is able to accurately describe the lithography process across the entire focus-exposure window. Moreover, a straightforward calibration without requiring excessive amount of through process window measurements is also critical to ensure quick turnaround-time.In this paper, we introduce a new Focus Exposure Matrix (FEM) model based on Brion's Tachyon™ platform. The FEM model has two adjustable parameters: focus and exposure. By adjusting these parameters, new models at arbitrary process conditions within the process window can be quickly derived, with which large number of simulation results can be obtained at different exposure and focus for detailed process window analysis. The fitting of FEM model is through a single calibration process using wafer measurements at limited number of sampling locations within the process window. The resulting calibrated FEM model is shown to have superior fitting as well as prediction accuracy, without requiring massive additional focus-exposure measurements.Accurate FEM modeling enables two important applications in the deep sub-wavelength regime: lithography manufacturability check (LMC) and optical proximity correction (OPC). FEM-enabled LMC proves to be a substantial advance in model-based verification by providing through process window analysis capability. Furthermore, FEMmodels can be employed in OPC practically to prevent catastrophic failures due to process variation while still maintaining satisfactory OPC quality in terms of matching the modeled wafer image to design intent.In this paper, we use real data and simulation results to demonstrate the quality of the FEM model and its effectiveness in the LMC and OPC applications.

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“…We built three preliminary defocus empirical models [4] to demonstrate this application based on a few sets of limited wafer data which were collected on the wafer printed at different focus conditions, one at defocus of -0.1um, one at defocus of +0.1um, and one at defocus of 0um. After three rounds of the model-based CD verification/prediction run on the same post-OPC layout, we obtained the CDE histograms vs. defocus as showed in Fig.7.…”

Section: Gate CD Verification At Defocus Conditionsmentioning

confidence: 99%

Full chip gate CD error prediction for model-based OPC

Shu¹,

Choi²,

Quek³

2005

Design and Process Integration for Microelectronic Manufacturing III

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In this paper, a technique for full chip gate CD(critical dimension) error prediction based on empirical models will be presented and discussed. In order to be compatible with existing common terminologies, this technique can also be called model-based full chip gate CD verification, which has become an integral part of closed-loop design-to-silicon flow of gate layer masking processes at 90nm and 65nm technology nodes. The empirical optical-and-process models can be same or different (such as with defocus) from the ones which are widely used in model based OPC and ORC. Similar to but different from conventional ORC, which normally addresses the minimum feature check or fatal error check, the model-based gate CD verification technique will focus on CD error prediction and CD error distribution analysis for gate CD related yield improvement efforts. Current commercial ORC or model-based verification tools provide the capability of EPE (edge placement error) check and analysis, and with certain additional techniques they may also provide the capability of gate CD prediction or simulation for selected targets or figures. The new model-based gate CD verification technique will provide the capability of full chip CD error prediction and CD error distribution analysis for all concerned small gate CD targets. INTROUCTIONFor low k1 lithography of advanced IC technology nodes at 90nm, 65nm and below, gate CD control is crucial to transistor functions and performances. While process variations, such as ACLV (across chip line-width variation), have been considered as the big contributors to gate CD variation and they can consume significant part of overall CD control budget, CD error budget for MBOPC (model based optical proximity/process correction), including model calibration and OPC correction, has been pushed to be as small as possible.With well-calibrated empirical OPC model, the main task of OPC correction is to fragment original layout edges in limited numbers and then move these fragments so that the EPE (edge placement errors) are minimized based on the optical-and-process model simulation. The various local specific features of the layout will have great impact on actual OPC fragmentation and OPC accuracy. In order to achieve the highest OPC accuracy, either OPC needs to be tuned and optimized for a specific layout design, or the layout design needs to be altered to cater for OPC limitations, which may need to go through a few cycles. For the both cases, model-based full chip CD error prediction has become inevitable OPC sign-off step or a feedback step in the close-looped design-to-silicon flows of 90nm and 65nm masking processes, especially for gate layers. In addition to these, model-based full chip CD error prediction would also be a necessary step if the amount or specific types of RET or OPC schemes need to be decided in the cases that RET & OPC accuracy, complexity, run-time and mask writing cost need to be analyzed and compromised.Put the above sequential steps and the feedback steps together, a simplifie...

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Calibration of OPC models for multiple focus conditions

Cited by 12 publications

References 5 publications

Through-process modeling in a DfM environment

Through-process modeling in a DfM environment

A focus exposure matrix model for full chip lithography manufacturability check and optical proximity correction

Full chip gate CD error prediction for model-based OPC

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