Capacitance Expressions and Electrical Characterization of Tapered Through- Silicon Vias for 3-D ICs

Abstract

Closed-form expressions of the parasitic insulator capacitance and the substrate capacitance for tapered throughsilicon vias (T-TSVs) are proposed. The expressions are suitable for TSVs with high aspect ratio (thin and long). The maximum percentage errors between the calculated and simulated results for the insulator capacitance and the substrate capacitance are 1.86% and 3.75%, respectively. Then the equivalent circuit model of the T-TSV signal-ground pair is established and validated by comparison with the full-wave simulation results. Furthermore, the electrical characteristics of the T-TSV are evaluated with the proposed expressions. The results indicate that the T-TSV has longer latency and less crosstalk than the cylindrical TSVs. Index Terms-Insulator capacitance, metal-oxidesemiconductor (MOS) effect, substrate capacitance, tapered through-silicon vias (T-TSVs).2156-3950 . Her current research interests include microwave and millimeter-wave integrated circuits, electromagnetic compatibility, and microstrip antenna.

Analysis of Eddy Effect for Cu and CNT Bundle Based Through-Silicon Vias: Impact on Crosstalk and Power

“…A silicon substrate capacitance ( ′ ) is formed between the TSVs due to the presence of conductive silicon substrate. The ′ can be derived using the parallel-wire capacitance model [29]…”

“…Liner capacitance ′ exists between the TSV and depletion layer due to the presence of the oxide layer [13]. In addition to this, depletion capacitance ′ formed between the TSVs surrounded by the oxide layer and the Si substrate in the presence of the depletion layer [29]. The ′ and ′ in p.u.h.…”

Transmission characteristics of multi‐walled carbon nanotube‐based through‐silicon vias considering temperature effects

“…Carbon nanotube (CNT) is the most promising material for very large scale integration interconnects in the future due to their extraordinary electrical, thermal and mechanical properties [1][2][3][4]. Through-silicon via (TSV) providing a vertical connection between chips is the primary technology in three-dimensional integrated circuits (3D ICs) [5][6][7][8]. To further improve the performance of 3D ICs, much research on CNT-based TSV has been done.…”

Admittance extraction and analysis for through silicon vias near edge and at corner of silicon substrate

“…In real case, however, the silicon substrate has a limited size in both vertical and horizontal directions. For vertical direction, the finite thickness of the silicon substrate (or the TSV height) has an impact on the parasitic parameters of the TSVs, which have been studied in [7][8][9][10][11]. For horizontal direction, the finite edge length of silicon substrate may also affect parasitic parameters of TSVs due to different TSV distributions, as shown in Fig.…”

“…The superscript mn and subscript ij relate to the boundary condition at the ith match point p on TSV m , due to the jth charge expansion function on TSV n and its image TSV n* , as shown in Fig. 3 ] can be calculated by (6) based on the boundary condition (ii) as (see (9) and 10)where r n = r n* = r tsv . l r (l r* ) and l θ (l θ* ) represent the projection of the two electric field unit vector on the normal direction of the dielectric surfaces.…”